How in Design Compiler disable writing out "Assign" statement into the netlist?

Discussion in 'VHDL' started by Frank, Jan 20, 2006.

  1. Frank

    Frank Guest

    I was aware that there is a flag which can disenable Design Compiler to
    write Assign statement. My NCVerilog gave me warning on Assign statement
    when performing gate level simulations.

    Many thanks in advance.
    Frank, Jan 20, 2006
    #1
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  2. Frank

    Ajeetha Guest

    Ajeetha, Jan 22, 2006
    #2
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  3. Frank

    Jerry Avins Guest

    Re: How in Design Compiler disable writing out "Assign" statementinto the netlist?

    Ajeetha wrote:
    > Frank,
    > See:
    >
    > http://www.deepchip.com/posts/0184.html
    >
    > HTH
    > Ajeetha
    > www.noveldv.com


    I love this quote: "It's always been my dream to give my customers a
    choice between ViewLogic & ViewLogic." That's a nice perch to sit on!

    Jerry
    --
    Engineering is the art of making what you want from things you can get.
    ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
    Jerry Avins, Jan 22, 2006
    #3
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