how to define a type with inputs and outputs like a bus

Discussion in 'VHDL' started by Aiken, Jul 23, 2012.

  1. Aiken

    Aiken Guest

    I would want to define a bus interface such that I can use it everywhere I need.

    I get into a trouble is I need to separate the input and output into two types.

    Is there a way to let it only need to declare it one time when I need the bus?


    type bus_in_type is record
    clk : std_ulogic ;
    enb : std_ulogic ;
    datain : std_ulogic ;
    end record bus_in_type ;

    type bus_out_type is record
    dataout : std_ulogic ;
    douten : std_ulogic ;
    end record bus_out_type ;
     
    Aiken, Jul 23, 2012
    #1
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  2. Aiken

    Tricky Guest

    On Monday, July 23, 2012 7:25:27 PM UTC+1, Aiken wrote:
    > I would want to define a bus interface such that I can use it everywhere I need.
    >
    >
    >
    > I get into a trouble is I need to separate the input and output into two types.
    >
    >
    >
    > Is there a way to let it only need to declare it one time when I need the bus?
    >
    >
    >
    >
    >
    > type bus_in_type is record
    >
    > clk : std_ulogic ;
    >
    > enb : std_ulogic ;
    >
    > datain : std_ulogic ;
    >
    > end record bus_in_type ;
    >
    >
    >
    > type bus_out_type is record
    >
    > dataout : std_ulogic ;
    >
    > douten : std_ulogic ;
    >
    > end record bus_out_type ;


    stick it in a package?
     
    Tricky, Aug 2, 2012
    #2
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  3. Am 23.7.2012 20:25, schrieb Aiken:

    > I would want to define a bus interface such that I can use it everywhere I need.


    > type bus_in_type is record
    > clk : std_ulogic ;
    > enb : std_ulogic ;
    > datain : std_ulogic ;
    > end record bus_in_type ;
    >
    > type bus_out_type is record
    > dataout : std_ulogic ;
    > douten : std_ulogic ;
    > end record bus_out_type ;


    Put the type declarations into a package and include the package
    everywhere you need it.

    Take care! Write to the record only in /one/ component. Do not try to
    write to one record element in one component and to another record
    element in a different component. The declared record type is an
    unresolved data type (unless you write a resolution function).
    => Such records are not really a bus. They are more a "tube" or a big
    "cable" where a lot of "wires" are included.

    Such recored "cables" work fine with synthesis (tested with Xilinx ISE,
    synopsys design analyzer).
    The biggest advantage of such "cables" is the fact, that they easy can
    be fed through several levels of hierarchy while changing one of the
    "wires", adding new "wires" and so on is really easy.

    Ralf
     
    Ralf Hildebrandt, Aug 6, 2012
    #3
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