How to get two different clock

Discussion in 'VHDL' started by Amit, Sep 23, 2007.

  1. Amit

    Amit Guest

    Hello group,

    Is this possible or does it make sense to create an element which its
    output become a clock of other elements of a circut? I need to clock
    two different entities. One gets a clock as milisecond and one as
    second!



    Thanks,
    Amit
     
    Amit, Sep 23, 2007
    #1
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  2. Amit

    Szymon Janc Guest

    Amit napisa³:

    > Is this possible or does it make sense to create an element which its
    > output become a clock of other elements of a circut? I need to clock
    > two different entities. One gets a clock as milisecond and one as
    > second!


    Use clock-enable signals to hold your elements. And read about 'gated
    clock' and problems connected with it.

    --
    Szymon K. Janc
    szymon#janc.int.pl // GG: 1383435
     
    Szymon Janc, Sep 23, 2007
    #2
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  3. > Is this possible or does it make sense to create an element which its
    > output become a clock of other elements of a circut? I need to clock
    > two different entities. One gets a clock as milisecond and one as
    > second!
    >

    There is no simple answer to this really. The purists will argue that such
    things should never be done. However, in the real-world it is in general OK
    providing a couple of facts are true:
    1. The technology you are using allows the generated clock to be distributed
    as if it was a normal external clock. In the case of FGPAs, this typically
    involves instantiating a global clock buffer to force the generated clock to
    be routed on dedicated clock routing nets.
    2. Your design doesn't rely on any timing relationship between the clocks.
    In other words, when interfacing between logic using the two clocks one
    needs to follow normal multi-clock domain procedures.

    Whether it's a good idea to use generated clocks or not is a different
    matter, and depends on what you are trying to do. If, for example, you have
    a design that features two unconnected blocks of logic - one running at
    100MHz and the other at 50MHz, it would make sense to generate the 50MHz
    clock by dividing the 100MHz one. However, in your case you are probably
    better running everything off the system clock and implementing a prescaler
    that generates a one-clock wide enable every millisecond (and another every
    second) that are then used to gate your low-speed entities.
     
    David Spencer, Sep 23, 2007
    #3
  4. Amit schrieb:


    > Is this possible or does it make sense to create an element which its
    > output become a clock of other elements of a circut? I need to clock
    > two different entities. One gets a clock as milisecond and one as
    > second!



    Clock gating is the key to low-power designs, but it is not simple as
    clock-skew and data transfer between clock domains has to be considered.

    Use clock buffers and clock constraints for your gated clocks, if
    available. If not use at least a constraint during synthesis.

    Even with only a clock constraint (and without a suitable clock buffer)
    it _may_ be possible to get a running design at a FPGA. But it will be
    very slow.

    If you don't need clock gating, try to avoid it.

    Ralf
     
    Ralf Hildebrandt, Sep 23, 2007
    #4
  5. Amit

    Amit Guest

    On Sep 23, 9:43 am, Ralf Hildebrandt <> wrote:
    > Amit schrieb:
    >
    > > Is this possible or does it make sense to create an element which its
    > > output become a clock of other elements of a circut? I need to clock
    > > two different entities. One gets a clock as milisecond and one as
    > > second!

    >
    > Clock gating is the key to low-power designs, but it is not simple as
    > clock-skew and data transfer between clock domains has to be considered.
    >
    > Use clock buffers and clock constraints for your gated clocks, if
    > available. If not use at least a constraint during synthesis.
    >
    > Even with only a clock constraint (and without a suitable clock buffer)
    > it _may_ be possible to get a running design at a FPGA. But it will be
    > very slow.
    >
    > If you don't need clock gating, try to avoid it.
    >
    > Ralf



    Thank you all for your response. To be honest with you, I'm still
    confused about the clock so please let me explain what I have
    understood so far then I will be more than happy if you corrent me:

    The most confusing part for me is the master clock. I think I have to
    create an entity as ent_CLOCK for instance? then defining some
    constraints for this clock someting like a counter to check number of
    clock pulses. Since it must divide the time in 1000 slices and send
    them to entity_1 indvidually and when its COUNTER = 1000 then it
    should clock the entity_2 too.

    Is my assumption right?

    Regards,
    Amit
     
    Amit, Sep 23, 2007
    #5
  6. Amit wrote:


    > The most confusing part for me is the master clock. I think I have to
    > create an entity as ent_CLOCK for instance?


    The master clock is a crystal oscillator soldered
    on the circuit board. It is just an input
    port to the synthesis entity.

    For simulation, I might model this in my testbench
    with a process using wait statements like this.

    begin -- process tb_clk
    clk_s <= '0';
    if now < rst_time then
    rst_s <= '1'; -- rst once with clk running
    else
    rst_s <= '0'; -- then low forever
    end if;
    if done_s then wait; end if; -- Stop clock
    wait for clk_cy/2; -- clock low
    clk_s <= '1';
    fixed_stim; -- auxiliary outputs
    wait for clk_cy/2; -- clock high
    end process tb_clk;

    for details see:
    http://home.comcast.net/~mike_treseler/

    > then defining some
    > constraints for this clock someting like a counter to check number of
    > clock pulses. Since it must divide the time in 1000 slices and send
    > them to entity_1 indvidually and when its COUNTER = 1000 then it
    > should clock the entity_2 too.


    The counter output is used as a clock *enable*,
    Not a clock. Here is an example:

    http://home.comcast.net/~mike_treseler/count_enable.vhd

    -- Mike Treseler
     
    Mike Treseler, Sep 23, 2007
    #6
  7. Amit

    Shannon Guest

    Amit might be trying to create a simple divided clock. Here is an
    example of one of the ten thousand ways of making a divided clock.
    This is a divide by 4 clock: (DIVISOR := 4)

    PROCESS (MClk, Reset)
    BEGIN
    IF (Reset = '1') THEN
    clk_per_cur <= (OTHERS => '0');
    ELSIF (rising_edge (MClk)) THEN
    clk_per_cur <= clk_per_next;
    END IF;
    END PROCESS;

    clk_per_next <= (OTHERS => '0') WHEN clk_per_cur = (DIVISOR-1) ELSE
    clk_per_cur + 1;


    Shannon
     
    Shannon, Sep 24, 2007
    #7
  8. Amit

    Amit Guest

    On Sep 24, 6:48 am, Shannon <> wrote:
    > Amit might be trying to create a simple divided clock. Here is an
    > example of one of the ten thousand ways of making a divided clock.
    > This is a divide by 4 clock: (DIVISOR := 4)
    >
    > PROCESS (MClk, Reset)
    > BEGIN
    > IF (Reset = '1') THEN
    > clk_per_cur <= (OTHERS => '0');
    > ELSIF (rising_edge (MClk)) THEN
    > clk_per_cur <= clk_per_next;
    > END IF;
    > END PROCESS;
    >
    > clk_per_next <= (OTHERS => '0') WHEN clk_per_cur = (DIVISOR-1) ELSE
    > clk_per_cur + 1;
    >
    > Shannon




    THANKS ALL FOR YOUR HELP. I TRULY APPRECIATE IT.

    REGARDS,
    AMIT
     
    Amit, Sep 25, 2007
    #8
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