How to handle a real number in order to transport it to output in std_logic_vector

Discussion in 'VHDL' started by thaosb, Apr 10, 2009.

  1. thaosb

    thaosb

    Joined:
    Mar 30, 2009
    Messages:
    2
    Hi everyone!

    I am a beginner in VHDL. Im trying to write a program for my study but I encounter a problem about type of data in VHDL.

    In my application, I have to convert a digital value to analog (specificly, convert digital value of current to analog (ampere)).

    In my program, I wite a function using VHDL to calculate the value of current. All calculations are concerned with REAL values. I want to use the return value of this function as the input of D to A converter. I know that the input of D to A converter must be an INTEGER. Therefore, the return value of my function should be STD_LOGIC_VECTOR or have the type suitable for D to A converter input.

    I really don't know how to handle the REAL values in my function in order to make the return value suitable for the input of D to A converter without losing the accuracy of the result of calculations. If I fail in handle the type of data, I can not get the correct conversion with D to A converter.

    Can anybody tell me the method to deal wiht my problem?

    Please help me.

    Thank you very much.
    thaosb, Apr 10, 2009
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. eneko
    Replies:
    2
    Views:
    2,940
    eneko
    Oct 20, 2004
  2. eNo
    Replies:
    2
    Views:
    15,360
    Hubble
    Aug 9, 2005
  3. Sudhir
    Replies:
    2
    Views:
    989
    David Bishop
    Mar 10, 2007
  4. Thomas Rouam
    Replies:
    6
    Views:
    1,102
  5. Will
    Replies:
    3
    Views:
    689
    JohnDuq
    Mar 20, 2009
Loading...

Share This Page