How could I output a real signal to std_logic_vector?

Discussion in 'VHDL' started by Will, Mar 9, 2009.

  1. Will

    Will Guest

    Hi all,

    I'm really new to VHDL. I need to output a real signal. How could I
    convert it to std_logic_vector? Or, could I output a real number
    BTW, is there any way that I could monitor variables during test bench
    simulation like debugging in other language?

    Thanks and bow.
    Will, Mar 9, 2009
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  2. JohnDuq


    Dec 9, 2008
    Well, first you need some definition for your 'real' signal. If you can define it as a std_logic_vector then you are done.

    signal clk_scaler : unsigned(20 downto 0);

    What is your definition of 'real'? Not 'imaginary' (1 + i1)?

    Yes, your test bench will let you see about anything that makes it through the compiler.
    JohnDuq, Mar 18, 2009
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  3. Ukanbal


    Mar 7, 2009
    in VHDL you can set your signal into any number. you can write any signed or unsigned number on it and your output signal will carry that value until you change it.

    the question regarding creating a real signal... if you are talking about actual signals such as sinusoid i do not think you can do that. you can create a squarewave which is a simple clock in VHDL but thats about it.
    Ukanbal, Mar 20, 2009
  4. JohnDuq


    Dec 9, 2008
    You can create a sinusoid by using a look up table.
    JohnDuq, Mar 20, 2009
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