How to implement Random function

Discussion in 'VHDL' started by Karthikeyan Subramaniyam, Feb 24, 2006.

  1. Hi all,
    I'm trying to port Verilog code to VHDL. In that I've $random system
    task in verilog code. Can anyone support me to implement in VHDL
    simplest way.

    ----
    reg seq;
    always
    begin
    #10 seq = $random;
    end
    ----

    like,

    signal seq : std_logic;
    .....

    Thanks & Regards,
    Karthik
     
    Karthikeyan Subramaniyam, Feb 24, 2006
    #1
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  2. Karthikeyan Subramaniyam wrote:
    > Hi all,
    > I'm trying to port Verilog code to VHDL. In that I've $random system
    > task in verilog code. Can anyone support me to implement in VHDL
    > simplest way.


    See the function "randomize" in the process tb_clk
    in the testbench here:

    http://home.comcast.net/~mike_treseler/test_uart.vhd


    -- Mike Treseler
     
    Mike Treseler, Feb 24, 2006
    #2
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  3. Karthikeyan Subramaniyam

    Barry Brown Guest

    Package IEEE.math.real defines a function uniform for random variables.


    "Karthikeyan Subramaniyam" <> wrote in message
    news:dtm45f$3u3$...
    > Hi all,
    > I'm trying to port Verilog code to VHDL. In that I've $random system
    > task in verilog code. Can anyone support me to implement in VHDL
    > simplest way.
    >
    > ----
    > reg seq;
    > always
    > begin
    > #10 seq = $random;
    > end
    > ----
    >
    > like,
    >
    > signal seq : std_logic;
    > ....
    >
    > Thanks & Regards,
    > Karthik
     
    Barry Brown, Feb 24, 2006
    #3
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