How to make Unconstrained std_logic_vector port :)

Discussion in 'VHDL' started by mido_nour1, Jul 29, 2009.

  1. mido_nour1

    mido_nour1

    Joined:
    Jul 29, 2009
    Messages:
    3
    hi all

    I really see alot of hard working here in this forum.
    This is my first time here with you and i am in the early stages of VHDL Learning
    :)... so please be patient with me :)

    This is a small problem i encountered when making a very simple adder/multiplier
    code::::

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

    ENTITY My_Entity IS
    port(
    a,b : in std_logic_vector(1 downto 0);
    c : in std_logic ;
    d : out std_logic_vector
    );
    END ENTITY My_Entity;

    --
    ARCHITECTURE Behave OF My_Entity IS
    BEGIN

    process (c)
    begin
    case c is
    when '0' => d <= a*b ;
    when others => d <= a+b;
    end case;

    end process;
    END ARCHITECTURE Behave;


    The problem is .. we all know that when we adding 2 vector 2 bits each, we may encounter a carry, so the output must be 3 bits......
    In the same time i wanna make a multiplier ( 2 vetors 2 bits each ), and we all know that the result "ouput" should be 4 bits wide...

    so i need the output vector ""d"" to be flexible with me .. accepting 3 bits when adding and accepting 4 bits when multiplying

    i have read before that i can do this :
    d : out std_logic_vector
    without specifying length of vector
    But in the Simulation Stage i get
    " FATAL Error : d port can't be unconstrained:


    SO WHAT Do u think i can do xD
    Thanks u all in advance
     
    mido_nour1, Jul 29, 2009
    #1
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  2. mido_nour1

    mido_nour1

    Joined:
    Jul 29, 2009
    Messages:
    3
    Hey Guys .. any Help :-(
     
    mido_nour1, Jul 30, 2009
    #2
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  3. mido_nour1

    mido_nour1

    Joined:
    Jul 29, 2009
    Messages:
    3
    Hey guys .. is this can't be done

    or

    am i too idiot to be replied on ??

    or

    what ??
     
    mido_nour1, Jul 31, 2009
    #3
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