Unconstrained array of unconstrained vector.

Discussion in 'VHDL' started by Amal, Mar 7, 2006.

  1. Amal

    Amal Guest

    Is there a way (in VHDL93) to define an array of vectors in a package
    and set the array size and vector size later? Basically, I would like
    to set the number of array elements and the vector sizes later (maybe
    using a function call). I know this could be done using an enity with
    generics like this:

    entity mem is
    generic (
    d : positive := 32;
    w : positive := 8
    );
    port (
    ...
    );
    end entity mem;

    architecture rtl of mem is

    type memType is array( 0 to d-1 ) of std_logic_vector( w-1 downto 0);
    signal memory : memType;

    begin
    end architecture rtl;

    But preferably, I would like to define the array in a package and
    provide public functions to set the array size and access routines.
    The advantage is having a set of packages with self contained routines
    that mimic the object-oriented (abstraction and data hiding) features
    of object-oriented langugaes. I know there is a VHDL-200x-FT proposal
    FT14 that includes partial and unconstrained array elements. But is
    there a way to do it using VHDL93?

    The following is a hypothetical example that would not compile!

    package my_pkg

    type arrayType is array( natural range <> ) of bit_vector( natural
    range <> );

    type memType is
    record
    d : integer;
    w : integer;
    memory : arrayType(0 to depth-1)( w-1 downto 0);
    -- or any other initialization routine to initialize a ROM
    -- := init(????)
    end record;

    procedure setMemSize( d: integer; w : integer );

    end package my_pkg;

    package body my_pkg is

    procedure setMemSize( signal mem: in memType; d: integer; w : integer
    ) is
    begin
    mem.d := d;
    mem.w := w;
    mem.memory <= (others=>(others=>'0');
    end procedure setMemSize;

    end package body my_pkg;

    -- Amal
    Amal, Mar 7, 2006
    #1
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  2. Amal wrote:
    > Is there a way (in VHDL93) to define an array of vectors in a package
    > and set the array size and vector size later?


    For synthesis, there is no "later".
    While I can declare generic or unconstrained types,
    constant lengths must be found for all variable
    and port objects by the end of elaboration.
    See:
    http://groups.google.com/groups/search?q=vhdl array vectors package unconstrained

    For simulation I can NEW and DEALLOCATE whatever I like.

    -- Mike Treseler
    Mike Treseler, Mar 7, 2006
    #2
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  3. Amal

    Amal Guest

    Amal, Mar 7, 2006
    #3
  4. Amal wrote:
    > Is there a way (in VHDL93) to define an array of vectors in a package
    > and set the array size and vector size later? Basically, I would like
    > to set the number of array elements and the vector sizes later (maybe
    > using a function call). I know this could be done using an enity with
    > generics like this:
    >
    > entity mem is
    > generic (
    > d : positive := 32;
    > w : positive := 8
    > );
    > port (
    > ...
    > );
    > end entity mem;
    >
    > architecture rtl of mem is
    >
    > type memType is array( 0 to d-1 ) of std_logic_vector( w-1 downto 0);
    > signal memory : memType;
    >
    > begin
    > end architecture rtl;


    I don't know any way to implement this directly, but one solution (or
    "workaround") is to use a package, where you first define constants
    for all the sizes you need, then use those to define types with
    correct widths. You can now include this package in all designs that
    work with those types or need to know the sizes. The main problem is,
    that all of those constants and types are now in the "global"
    namespace (since most units will need to access that package). But
    that can be solved with reasonable naming conventions.

    Works perfectly for synthesis and of course simulation.

    Beware of complex types for synthesis though, there can be unexpected
    pitfalls (at least certain releases of synopsys had a problem with
    complex aggregate constructs used for constant initialization, for
    example).

    Also avoid "complex" types (i.e. anything other than std_logic or
    one-dimensional std_logic_vectors) on top-level ports, since it
    usually leads to problems in later flow stages (e.g. with verilog
    netlists, ...).

    HTH, Robert


    PS: the problem is, that generics are not locally static and can
    therefore not be used for port size allocation, if I remember
    correctly.
    Robert Reutemann, Mar 8, 2006
    #4
  5. Amal

    Andy Guest

    Defining the array width/depth in a package based on constants will
    work, but is not customizable on the command line like most simulators
    and synthesizers will allow you to do with top level generics.
    Unfortunately, until the next version of vhdl, packages cannot use
    generics.

    Another option is to create the array at some convenient level of the
    hierarchy (in a parent of any modules that will need it), and pass it
    on a port to them. This allows a generic to control the size
    (width/depth) of the structure, and therefore it can be set via the
    command line without altering source code.

    I'm not aware of any restrictions in defining port sizes on entities
    based on generics; I do it all the time.

    Andy Jones
    Andy, Mar 8, 2006
    #5
  6. Amal

    Brandon Guest

    There is currently no clean way to do this with generics as you want. I
    find this really annoying, but hopefully the standards committee and
    vendors adopt this in the future...

    What you can also do is create unwrapped arrays of standard logic
    vectors. Instead of an array of 'd' vectors of length 'w', use one 'd'
    * 'w' length vector.
    Brandon, Mar 8, 2006
    #6
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