Hello, I have a problem with the following construct:
process(clk, reset_n)
begin
if (reset_n = '0') then
out <= '0';
elsif (clk'event and clk = '1') then
if (clear = '1') then
out <= '0';
elsif (set = '1') then
out <= '1';
end if;
end if;
end process;
I have synthesized this for a xilinx. Although the signal "set" is observed to be completely fixed at '0' (in logic analyzer), I get a transition from 0 to 1 on "out". Could it be a glitch on "set" ? Is this a problematic construction for some reason?
process(clk, reset_n)
begin
if (reset_n = '0') then
out <= '0';
elsif (clk'event and clk = '1') then
if (clear = '1') then
out <= '0';
elsif (set = '1') then
out <= '1';
end if;
end if;
end process;
I have synthesized this for a xilinx. Although the signal "set" is observed to be completely fixed at '0' (in logic analyzer), I get a transition from 0 to 1 on "out". Could it be a glitch on "set" ? Is this a problematic construction for some reason?