if/elsif problem

Discussion in 'VHDL' started by karlwijk, Apr 16, 2007.

  1. karlwijk

    karlwijk

    Joined:
    Apr 16, 2007
    Messages:
    2
    Hello, I have a problem with the following construct:

    process(clk, reset_n)
    begin
    if (reset_n = '0') then
    out <= '0';
    elsif (clk'event and clk = '1') then
    if (clear = '1') then
    out <= '0';
    elsif (set = '1') then
    out <= '1';
    end if;
    end if;
    end process;

    I have synthesized this for a xilinx. Although the signal "set" is observed to be completely fixed at '0' (in logic analyzer), I get a transition from 0 to 1 on "out". Could it be a glitch on "set" ? Is this a problematic construction for some reason?
    karlwijk, Apr 16, 2007
    #1
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  2. karlwijk

    quantum_dot

    Joined:
    Nov 21, 2006
    Messages:
    31
    if/elsif statement !

    Well, this coding is similar to C programming, and may create a problem in actual hardware. You have not specified all the possible conditions for set/clear. May be you can give this a try :

    process(clk, reset_n)
    begin
    if (reset_n = '0') then
    out <= '0';
    elsif (clk'event and clk = '1') then
    if (clear = '1' and set = '0') then
    out <= '0';
    elsif (clear = '0' and set = '1') then
    out <= '1';
    end if;
    end if;
    end process;
    quantum_dot, Apr 17, 2007
    #2
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  3. karlwijk

    karlwijk

    Joined:
    Apr 16, 2007
    Messages:
    2
    Hi, thanks. Can you explain why my solution creates a problem? Under what signal conditions? Is it, for instance, if you get clear='1' and set='1' at the same time?

    Kind regards,
    Karl

    karlwijk, Apr 17, 2007
    #3
  4. karlwijk

    quantum_dot

    Joined:
    Nov 21, 2006
    Messages:
    31
    Not specifying all the conditions for "clear" or "set" results in a latch condition, which you are not aiming for. This may result in a unpredicted metastable state, which is causing the problem.
    :driver:
    quantum_dot, Apr 18, 2007
    #4
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