Importing a Xilinx system generator design into a bigger system

[boysr2003]

Hi my name is Yassir Boukhriss, and i am currently using Xilinx
System Generator. I generated the vhdl code for my system generator
design and included the generated ngc file in my top level code
directory. I instatiated my sys gen design in the top level code, and
in the port map, i connected the inputs and outputs from the sysgen
design to the appropriate inputs and outputs of the top level code.
The instantiation and the port map are listed below. After i download
the code into the board, and look at the output that is supposed to
be driven by Sysgen, i get a constant, meaning that sysgen is not
passing anything through. Has anyone tried something like that, or
can anyone take a look at my code and tell me if i missing something.
Thanks
Yassir.

component little_test_clk_wrapper port(
ce: in std_logic :='1';
ce_clr : in std_logic :='0';
clk: in std_logic;
gateway_in1: in std_logic_vector(31 downto 0);
gateway_out1: out std_logic_vector(31 downto 0);
gateway_out2: out std_logic_vector(31 downto 0));
end component;

attribute box_type of little_test_clk_wrapper: component is
"black_box";
attribute syn_black_box of little_test_clk_wrapper: component is
true;
signal ce: std_logic :='1';
signal ce_clr: std_logic :='0';
0);

test: little_test_clk_wrapper

port map(
ce => '1',
ce_clr => '0',
clk => sample_clk,
gateway_in1 => gc0c_i_data,
--gateway_in2 => gc0c_q_data,
gateway_out1 => gc0c_i_data_b,
gateway_out2 => gc0c_q_data_b);