In VHDL testbench, how do I probe internal signal of an entity?

Discussion in 'VHDL' started by G Iveco, Jul 22, 2007.

  1. G Iveco

    G Iveco Guest

    In Verilog, I would do

    assign my_probe = i_mydesign.i_submodule.mult_en;

    I checked my textbooks but difficult to find equivalents in VHDL.

    Thanks in advance.
     
    G Iveco, Jul 22, 2007
    #1
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  2. G Iveco

    G Iveco Guest

    Does VHDL support `include statement?

    I was used to write tables and functions in a separate file and use `include
    in
    verilog design, in order to "put everything in single file" while avoiding
    large
    filesizes, one example is 1000+-line look-up tables.
     
    G Iveco, Jul 22, 2007
    #2
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  3. G Iveco

    HT-Lab Guest

    "G Iveco" <> wrote in message
    news:f7uhrh$l0l$...
    > In Verilog, I would do
    >
    > assign my_probe = i_mydesign.i_submodule.mult_en;
    >
    > I checked my textbooks but difficult to find equivalents in VHDL.
    >
    > Thanks in advance.


    Hierarchical references will be supported in the upcoming VHDL2006, see Jim
    Lewis presentation at
    http://www.synthworks.com/papers/vhdl_accellera_lewis_marlug_2006_color.pdf

    Most, if not all simulator have some non-standard support for this, if you
    are using Modelsim then have a look at signalspy,

    Hans
    www.ht-lab.com



    >
    >
     
    HT-Lab, Jul 22, 2007
    #3
  4. G Iveco

    HT-Lab Guest

    "G Iveco" <> wrote in message
    news:f7uk1n$l2c$...
    > Does VHDL support `include statement?
    >
    > I was used to write tables and functions in a separate file and use
    > `include in
    > verilog design, in order to "put everything in single file" while avoiding
    > large
    > filesizes, one example is 1000+-line look-up tables.


    Look up library, use and package in your VHDL textbook (or google)

    Hans
    www.ht-lab.com

    >
    >
    >
     
    HT-Lab, Jul 22, 2007
    #4
  5. G Iveco

    Guest

    On Jul 22, 10:17 am, "G Iveco" <> wrote:
    > Does VHDL support `include statement?
    >
    > I was used to write tables and functions in a separate file and use `include
    > in
    > verilog design, in order to "put everything in single file" while avoiding
    > large
    > filesizes, one example is 1000+-line look-up tables.



    VHDL doesn't support 'include .However google "vunit" .This might
    help.

    Probing of internal signals is also not supported by the language but
    individual simulators provide this function.
    For ModelSim, google "SingalSpy".
    For NcSim, google "nc_mirror"

    regards,
    Anupam Jain
     
    , Jul 23, 2007
    #5
  6. wrote:
    > On Jul 22, 10:17 am, "G Iveco" <> wrote:
    >> Does VHDL support `include statement?
    >>
    >> I was used to write tables and functions in a separate file and use `include
    >> in
    >> verilog design, in order to "put everything in single file" while avoiding
    >> large
    >> filesizes, one example is 1000+-line look-up tables.

    >
    >
    > VHDL doesn't support 'include .However google "vunit" .This might
    > help.
    >
    > Probing of internal signals is also not supported by the language but
    > individual simulators provide this function.
    > For ModelSim, google "SingalSpy".
    > For NcSim, google "nc_mirror"


    As an alternative, you could consider placing the signal in a package, and use
    that package both in your design and in your test bench/case.

    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Jul 23, 2007
    #6
  7. G Iveco

    HT-Lab Guest

    <> wrote in message
    news:...
    > On Jul 22, 10:17 am, "G Iveco" <> wrote:
    >> Does VHDL support `include statement?
    >>
    >> I was used to write tables and functions in a separate file and use
    >> `include
    >> in
    >> verilog design, in order to "put everything in single file" while
    >> avoiding
    >> large
    >> filesizes, one example is 1000+-line look-up tables.

    >
    >
    > VHDL doesn't support 'include .However google "vunit" .This might
    > help.


    vunit? that is PSL,

    Hans
    www.ht-lab.com


    >
    > Probing of internal signals is also not supported by the language but
    > individual simulators provide this function.
    > For ModelSim, google "SingalSpy".
    > For NcSim, google "nc_mirror"
    >
    > regards,
    > Anupam Jain
    >
     
    HT-Lab, Jul 23, 2007
    #7
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