Infix operator "+" Error

Discussion in 'VHDL' started by wadia, Sep 16, 2008.

  1. wadia

    wadia

    Joined:
    Sep 15, 2008
    Messages:
    2
    Hi everybody,

    I'm getting the following error:
    No feasible entries for infix operator "+"

    The program is as follow:
    -- Fichier : Compteur_bcd10.vhdl
    -- Description : Compteur BCD de 0 à 9
    library IEEE;
    use IEEE.std_logic_1164.all;
    -- use IEEE.numeric_std.all;

    entity compteur_bcd10 is -- définition des entrées/sorties
    port(clk, en, rst_n : in std_logic;
    rco : out std_logic;
    q : out std_logic_vector(3 downto 0));
    end compteur_bcd10;

    architecture behav of compteur_bcd10 is
    signal cnt : std_logic_vector(3 downto 0); --std_logic_vector(3 downto 0); -- signal interne
    begin
    q <= cnt; -- q, la sortie vaut la valeur du compte actuel en tout temps
    process(clk, rst_n) -- process sensible à l'horloge et au "clear"
    begin
    if (rst_n='0') then -- "clear" asynchrone
    cnt <= (others => '0');
    rco <= '0';
    elsif (clk'event and clk='1') then -- au front montant
    if (en='1') then -- si enable vaut 1
    if (cnt = "1010") then -- si on atteint 9, on fait un rco
    cnt <= (others => '0'); -- et on remet le compteur a 0
    rco <= '1';
    else -- sinon, on compte
    "ERROR LINE" cnt <= cnt + "0001";
    rco <= '0';
    end if;
    else
    cnt <= cnt;
    rco <= '0';
    end if;
    end if;
    end process;
    end behav;

    Could you please help me with this?

    Thanks & Regards,

    Walter

    Note: I've tried using unsigned, but the error is still there.
    wadia, Sep 16, 2008
    #1
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  2. wadia

    wadia

    Joined:
    Sep 15, 2008
    Messages:
    2
    Solution to No feasible entries for infix operator "+"

    I've found the solution to this problem by adding the following line to my program:

    use IEEE.std_logic_unsigned.all;

    That's it !

    Thanks anyway.
    wadia, Sep 16, 2008
    #2
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