inout to inout

Discussion in 'VHDL' started by Ken, May 9, 2008.

  1. Ken

    Ken Guest

    Quick question: is it possible to have a scenario where you can use an
    FPGA as a true bidirectional pipe without caring about the direction?
    I'm referring to problem below:

    entity true_bidir is
    port ( io_a : inout : std_logic;
    io_b : inout : std_logic
    );

    end entity;

    architecture bidir_arch of true_bidir is

    begin

    io_a <= io_b;
    io_b <= io_a;

    end architecture;

    This will not map (not even through Synplicity), because I'm getting
    an error saying, hey, you need a buffer or register between these
    pins. So, is it possible with some kind of code trick to allow a true
    bidirectional pipe through an FPGA? I don't care about a direction. I
    would think, in theory, you could map a 'Z' to a 'Z' and thus not
    worry about a buffer. I'm using a Virtex 4.

    Thanks

    Ken
    Ken, May 9, 2008
    #1
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  2. "Ken" <> wrote in message
    news:...
    > Quick question: is it possible to have a scenario where you can use an
    > FPGA as a true bidirectional pipe without caring about the direction?
    > I'm referring to problem below:
    >
    > entity true_bidir is
    > port ( io_a : inout : std_logic;
    > io_b : inout : std_logic
    > );
    >
    > end entity;
    >
    > architecture bidir_arch of true_bidir is
    >
    > begin
    >
    > io_a <= io_b;
    > io_b <= io_a;
    >
    > end architecture;
    >
    > This will not map (not even through Synplicity), because I'm getting
    > an error saying, hey, you need a buffer or register between these
    > pins. So, is it possible with some kind of code trick to allow a true
    > bidirectional pipe through an FPGA? I don't care about a direction. I
    > would think, in theory, you could map a 'Z' to a 'Z' and thus not
    > worry about a buffer. I'm using a Virtex 4.
    >
    > Thanks
    >
    > Ken
    >
    >


    Simple answer is no - you need to know what direction the signal is at any
    one time to control the I/O buffers. If you can't understand why, run the
    FPGA Editor within ISE and look at the schematic of an IOB (or look it up in
    the data sheet).
    David Spencer, May 9, 2008
    #2
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  3. Ken

    Aiken Guest

    you cannot use inout internally.

    On May 8, 8:46 pm, Ken <> wrote:
    > Quick question: is it possible to have a scenario where you can use an
    > FPGA as a true bidirectional pipe without caring about the direction?
    > I'm referring to problem below:
    >
    > entity true_bidir is
    > port ( io_a : inout : std_logic;
    > io_b : inout : std_logic
    > );
    >
    > end entity;
    >
    > architecture bidir_arch of true_bidir is
    >
    > begin
    >
    > io_a <= io_b;
    > io_b <= io_a;
    >
    > end architecture;
    >
    > This will not map (not even through Synplicity), because I'm getting
    > an error saying, hey, you need a buffer or register between these
    > pins. So, is it possible with some kind of code trick to allow a true
    > bidirectional pipe through an FPGA? I don't care about a direction. I
    > would think, in theory, you could map a 'Z' to a 'Z' and thus not
    > worry about a buffer. I'm using a Virtex 4.
    >
    > Thanks
    >
    > Ken
    >
    Aiken, May 9, 2008
    #3
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