internal signal delay problem

Discussion in 'VHDL' started by JohnSmith, Oct 5, 2012.

  1. JohnSmith

    JohnSmith Guest

    Hi,

    I have this cell in the sdf file

    (CELL (CELLTYPE "X_FF")
    (INSTANCE srl_q_9)
    (DELAY
    (ABSOLUTE
    (PORT CE ( 987 )( 987 ))
    (PORT CLK ( 111 )( 111 ))
    (PORT I ( 37 )( 37 ))
    (IOPATH CLK O ( 235 )( 235 ))
    )
    )
    (TIMINGCHECK
    (PERIOD (posedge CLK) (818))
    (SETUPHOLD(posedge CE) (posedge CLK) (115)(-5))
    (SETUPHOLD(negedge CE) (posedge CLK) (115)(-5))
    (SETUPHOLD(posedge I) (posedge CLK) (-14)(152))
    (SETUPHOLD(negedge I) (posedge CLK) (-14)(152))
    (RECREM(negedge SET) (posedge CLK) (277)(277))
    (RECREM(negedge RST) (posedge CLK) (207)(207))
    )
    )


    After running 100 fs in ModelSim, I have got this values in the
    instance

    ticd_CLK = 14 ps
    tisd_CE_CLK = 19 ps
    tisd_I_CLK = 0 ps // ???
    tisd_RST_CLK = 14 ps
    tisd_SET_CLK = 14 ps

    After studying "8.2.2.1 Calculation of internal clock delays" and
    "8.2.2.2 Calculation of internal signal delays" from "IEEE Standard
    for VITAL ASIC (Application Specific Integrated Circuit) Modeling
    Specification"

    I dont understand why "tisd_I_CLK = 0 ps".


    Thanks
     
    JohnSmith, Oct 5, 2012
    #1
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