Interview questions ;)

Discussion in 'VHDL' started by Clemens Blank, Feb 21, 2008.

  1. Hi

    I just came across some interview questions for digital design, and
    would like to discuss my solutions with you!

    #Design a circuit to divide input frequency by 2
    I could do this with a Toggle Flip flop where the inverted output
    is connected to the input, then i also divide the clock frequency by two

    # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle.
    I was thinking of having here a statemachine that outputs for 3 cycles
    0, and then it changes the state to output 3 times a 1 at each clock
    transition.

    # Which one is superior: Asynchronous Reset or Synchronous Reset

    Cleary this is the asynchronous reset but not sure why ;)

    Feedback or other questions would be interesting. Could be fun!
     
    Clemens Blank, Feb 21, 2008
    #1
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  2. > Cleary this is the asynchronous reset but not sure why ;)

    Not clear at all. This question is more of a trick. Neither reset type is
    superior.
    Each has it's benefits and negatives. Depending on your final target
    application and technology the strength for one type versus the other will
    be greater.

    Take a look on the comp.lang.fpga board, some of the very knowledgable users
    highley recommned not using async resets when targeting FPGAs. To make
    things even more interesting, you can code the design for a Xilinx fpga with
    no resets at all, making use of the fact that when the FPGA resets and
    reloads the program the FF and memories are in known states.

    Your other solutions are heading the right direction. Since you are asking
    on the comp.lang.vhdl board. I suggest you code a divide-by-n sequencial
    vhdl circuit and let the synthesizer do it's job.

    "Clemens Blank" <> wrote in message
    news:fpkvep$6u0$...
    > Hi
    >
    > I just came across some interview questions for digital design, and would
    > like to discuss my solutions with you!
    >
    > #Design a circuit to divide input frequency by 2
    > I could do this with a Toggle Flip flop where the inverted output
    > is connected to the input, then i also divide the clock frequency by two
    >
    > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle.
    > I was thinking of having here a statemachine that outputs for 3 cycles 0,
    > and then it changes the state to output 3 times a 1 at each clock
    > transition.
    >
    > # Which one is superior: Asynchronous Reset or Synchronous Reset
    >
    > Cleary this is the asynchronous reset but not sure why ;)
    >
    > Feedback or other questions would be interesting. Could be fun!
     
    Dwayne Dilbeck, Feb 21, 2008
    #2
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  3. On 21 Feb., 22:54, Clemens Blank <> wrote:
    > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle.
    > I was thinking of having here a statemachine that outputs for 3 cycles
    > 0, and then it changes the state to output 3 times a 1 at each clock
    > transition.


    You describe a divide by 6 cirquit.
    A divide by 3 with 50% duty cycle means for a 1 MHZ clk (1us periode),
    you generate 3 us periode with 1500 ns high and 1500 ns low. You need
    additional cornerstones to achieve this. Either you have a reliable
    clock double circuit available (eg. DLL) to generate a 2 MHZ clock and
    divide this by 6, or you have already 50% duty cycle and use rising
    and falling edge of the clock. Second sollution requires you to be
    aware of glitches.



    > # Which one is superior: Asynchronous Reset or Synchronous Reset


    Trick question.

    bye Thomas
     
    Thomas Stanka, Feb 22, 2008
    #3
  4. Thomas Stanka schrieb:
    > On 21 Feb., 22:54, Clemens Blank <> wrote:
    >> # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle.
    >> I was thinking of having here a statemachine that outputs for 3 cycles
    >> 0, and then it changes the state to output 3 times a 1 at each clock
    >> transition.

    >
    > You describe a divide by 6 cirquit.
    > A divide by 3 with 50% duty cycle means for a 1 MHZ clk (1us periode),
    > you generate 3 us periode with 1500 ns high and 1500 ns low. You need
    > additional cornerstones to achieve this. Either you have a reliable
    > clock double circuit available (eg. DLL) to generate a 2 MHZ clock and
    > divide this by 6, or you have already 50% duty cycle and use rising
    > and falling edge of the clock. Second sollution requires you to be
    > aware of glitches.


    Idea:
    to divide a clock by 3 initialise two 3-bit ringregisters with "110" and
    clock the first with rising edge, the second with falling edge. Then
    combine both LSBs with AND => The generated clock will be symmetrical
    and glitch free!

    Similar divide by 5

    Best regards

    Wolfgang
     
    Wolfgang Grafen, Feb 22, 2008
    #4
  5. Hi Wolfgang,

    On 22 Feb., 15:18, Wolfgang Grafen <>
    wrote:
    > Thomas Stanka schrieb:
    > > divide this by 6, or you have already 50% duty cycle and use rising
    > > and falling edge of the clock. Second sollution requires you to be
    > > aware of glitches.

    >
    > Idea:
    > to divide a clock by 3 initialise two 3-bit ringregisters with "110" and
    > clock the first with rising edge, the second with falling edge. Then
    > combine both LSBs with AND => The generated clock will be symmetrical
    > and glitch free!


    This is a good[1] sollution to be glitch free, but how could you
    obtain a symetrical clock, if your master clock is not symetrical?

    bye Thomas

    [1] for designs operating in "normal" environment
     
    Thomas Stanka, Feb 25, 2008
    #5
  6. Thomas Stanka schrieb:
    > Hi Wolfgang,
    >
    > On 22 Feb., 15:18, Wolfgang Grafen <>
    > wrote:
    >> Thomas Stanka schrieb:
    >>> divide this by 6, or you have already 50% duty cycle and use rising
    >>> and falling edge of the clock. Second sollution requires you to be
    >>> aware of glitches.

    >> Idea:
    >> to divide a clock by 3 initialise two 3-bit ringregisters with "110" and
    >> clock the first with rising edge, the second with falling edge. Then
    >> combine both LSBs with AND => The generated clock will be symmetrical
    >> and glitch free!

    >
    > This is a good[1] sollution to be glitch free, but how could you
    > obtain a symetrical clock, if your master clock is not symetrical?
    >

    Yes, master clock has to be symmetrical. If not and you need a symmetrical
    output clock then you could make input or output clock symmetrical e.g.
    by means of a PLL.

    Wolfgang
     
    Wolfgang Grafen, Feb 25, 2008
    #6
  7. Thomas Stanka schrieb:


    > You describe a divide by 6 cirquit.
    > A divide by 3 with 50% duty cycle means for a 1 MHZ clk (1us periode),
    > you generate 3 us periode with 1500 ns high and 1500 ns low. You need
    > additional cornerstones to achieve this. Either you have a reliable
    > clock double circuit available (eg. DLL) to generate a 2 MHZ clock and
    > divide this by 6, or you have already 50% duty cycle and use rising
    > and falling edge of the clock. Second sollution requires you to be
    > aware of glitches.


    The 2nd solution is a tricky one, but at the end a solution with few
    hardware ressources. One can use a Pseudo-Dual-Edge D-Flipflop:
    <http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf> and
    <http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.vhd>.


    >> # Which one is superior: Asynchronous Reset or Synchronous Reset

    >
    > Trick question.


    Yes. Both of them have advanteages and disadvantes.

    Ralf
     
    Ralf Hildebrandt, Feb 29, 2008
    #7
  8. Clemens Blank

    Peter Guest

    > This is a good[1] sollution to be glitch free, but how could you
    > obtain a symetrical clock, if your master clock is not symetrical?
    >


    Its not so bad:

    A master clock with a 45/55 ratio gives 48/52 as a divide by 3 output.
    30/70 gives 43/57. So even if the output clock is not exactly
    symmetrical,
    its better than the input clock.

    /Peter
     
    Peter, Mar 6, 2008
    #8
  9. On 6 Mrz., 13:41, Peter <> wrote:
    > > This is a good[1] sollution to be glitch free, but how could you
    > > obtain a symetrical clock, if your master clock is not symetrical?

    >
    > Its not so bad:
    >
    > A master clock with a 45/55 ratio gives 48/52 as a divide by 3 output.
    > 30/70 gives 43/57. So even if the output clock is not exactly
    > symmetrical,
    > its better than the input clock.


    You are right, but the question was for a 50% duty cycle (Interview
    question, however my colleque has a design that wouldn't be in spec,
    if the external duty cycle varies more than 1% as the DDR output would
    be out of window).

    bye Thomas
     
    Thomas Stanka, Mar 7, 2008
    #9
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