Is there delta=0 except at the beginning moment?

Discussion in 'VHDL' started by fl, Sep 11, 2011.

  1. fl

    fl Guest

    Hi,
    I find that only at the simulation beginning that delta =0. Other time
    it is at least +1, or larger. I want to know that it is possible that
    delta=0 in the middle of simulation?

    Thanks.
     
    fl, Sep 11, 2011
    #1
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  2. fl wrote:

    > Hi,
    > I find that only at the simulation beginning that delta =0. Other time
    > it is at least +1, or larger. I want to know that it is possible that
    > delta=0 in the middle of simulation?


    A late reply.

    I suppose you only see deltas larger than zero because you put break points
    in synthesisable code. In general, these are processes that wake up on
    signal events. Primary input signals generated in a testbench (such as a
    clock) usually change at times with a delta=1. Other signals after that, so
    delta >= 2.

    Take for example a clock generator:

    clk_gen: clk <= NOT clk AFTER half_clk_period;

    Or:

    clk_gen: PROCESS IS
    BEGIN
    WAIT for half_clk_period;
    clk <= NOT clk;
    END PROCESS clk_gen;

    Put a break point on the line "clk <= NOT clk;" in the process and you'll
    see times that are multiples of half_clk_period, all with delta=0.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
     
    Paul Uiterlinden, Oct 12, 2011
    #2
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