"Large" memory array in VHDL

Discussion in 'VHDL' started by Alex, Jul 5, 2006.

  1. Alex

    Alex Guest

    My application needs a somewhat large memory array, for constant (every
    clock cycle) sequential read/write access -- the size in question is
    exactly 64KB (524288 bits).

    Is a memory block of this size reasonable / possible to do in just
    VHDL? My FPGA in question is a Spartan-3E, and we have not yet decided
    upon the exact package yet.

    If this task is not feasible in VHDL alone, what external RAM device
    might be recommended? Having the VHDL for access to such an external
    RAM available for reference would be a big boon here.

    A side note on how this memory block will be used. One "task" will be
    iterating over the block repeatedly, with data trickling in replacing
    old values -- so each incoming byte stored in the RAM will be accessed
    many times before it is overwritten.

    Any tips or links to materials regarding this would be greatly
    appreciated.

    Thank you.

    Alex McHale
     
    Alex, Jul 5, 2006
    #1
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  2. Alex

    radarman Guest

    Alex wrote:
    > My application needs a somewhat large memory array, for constant (every
    > clock cycle) sequential read/write access -- the size in question is
    > exactly 64KB (524288 bits).
    >
    > Is a memory block of this size reasonable / possible to do in just
    > VHDL? My FPGA in question is a Spartan-3E, and we have not yet decided
    > upon the exact package yet.
    >
    > If this task is not feasible in VHDL alone, what external RAM device
    > might be recommended? Having the VHDL for access to such an external
    > RAM available for reference would be a big boon here.
    >
    > A side note on how this memory block will be used. One "task" will be
    > iterating over the block repeatedly, with data trickling in replacing
    > old values -- so each incoming byte stored in the RAM will be accessed
    > many times before it is overwritten.
    >
    > Any tips or links to materials regarding this would be greatly
    > appreciated.
    >
    > Thank you.
    >
    > Alex McHale


    If you want to do it all internally, the only part big enough is the
    XC3S1600E. However, you could simply plop on an external SRAM, have
    enough RAM left over for growth, and get by with a MUCH smaller FPGA.
    Even better would be an appropriately sized external dual-port RAM.
    This would allow you to just implement your control logic and data
    interface in the FPGA, which (depending on your application) could be a
    much smaller device.

    FPGA's make for some very expensive RAM. If you need RAM in bulk, it's
    generally better to just add RAM unless you have some other constraint
    that forbids it.
     
    radarman, Jul 5, 2006
    #2
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  3. Alex

    Alex Guest

    radarman wrote:
    > If you want to do it all internally, the only part big enough is the
    > XC3S1600E. However, you could simply plop on an external SRAM, have
    > enough RAM left over for growth, and get by with a MUCH smaller FPGA.
    > Even better would be an appropriately sized external dual-port RAM.
    > This would allow you to just implement your control logic and data
    > interface in the FPGA, which (depending on your application) could be a
    > much smaller device.
    >
    > FPGA's make for some very expensive RAM. If you need RAM in bulk, it's
    > generally better to just add RAM unless you have some other constraint
    > that forbids it.


    This is along the lines of what I expected. Dual port ram is
    definitely a possibility, do you have any suggestions as to a part?
    Like I said, I'd be looking for a minimum of 64KB. On one side of the
    DP RAM would be the Spartan-3E, and on the other would be a NetBurner
    module (a pretty average microcontroller).

    Thank you!

    Alex McHale
     
    Alex, Jul 5, 2006
    #3
  4. Alex

    Peter Alfke Guest

    The XC3S1500 has enough (576 K bits) of dual-ported RAM inside the
    FPGA. You decide whether that is economical or not. External SRAM need
    not be dual-ported, can be single-ported, if you have enough
    nanoseconds to time-multiplex. I believe external dual-ported RAM is
    exotic and expensive. Internal BlockRAM is dual-ported "for free".
    Peter Alfke, Xilinx
    ============
    Alex wrote:
    > My application needs a somewhat large memory array, for constant (every
    > clock cycle) sequential read/write access -- the size in question is
    > exactly 64KB (524288 bits).
    >
    > Is a memory block of this size reasonable / possible to do in just
    > VHDL? My FPGA in question is a Spartan-3E, and we have not yet decided
    > upon the exact package yet.
    >
    > If this task is not feasible in VHDL alone, what external RAM device
    > might be recommended? Having the VHDL for access to such an external
    > RAM available for reference would be a big boon here.
    >
    > A side note on how this memory block will be used. One "task" will be
    > iterating over the block repeatedly, with data trickling in replacing
    > old values -- so each incoming byte stored in the RAM will be accessed
    > many times before it is overwritten.
    >
    > Any tips or links to materials regarding this would be greatly
    > appreciated.
    >
    > Thank you.
    >
    > Alex McHale
     
    Peter Alfke, Jul 5, 2006
    #4
  5. Alex

    Nial Stewart Guest

    > This is along the lines of what I expected. Dual port ram is
    > definitely a possibility, do you have any suggestions as to a part?
    > Like I said, I'd be looking for a minimum of 64KB. On one side of the
    > DP RAM would be the Spartan-3E, and on the other would be a NetBurner
    > module (a pretty average microcontroller).



    Alex, what sort of clock speed is the uC running at?

    One solution is to pipeline the uC access to the ram through the FPGA
    then alternate access between the uC interface and the FPGA process
    that's doing the clever bits.

    If the uC clock is slow this becomes much easier to implement.


    Nial
     
    Nial Stewart, Jul 5, 2006
    #5
  6. Alex

    Ricardo Guest

    http://www.google.com/search?hl=pt-BR&q=xilinx using block ram

    It depends on the size of your fpga.

    Alex escreveu:

    > My application needs a somewhat large memory array, for constant (every
    > clock cycle) sequential read/write access -- the size in question is
    > exactly 64KB (524288 bits).
    >
    > Is a memory block of this size reasonable / possible to do in just
    > VHDL? My FPGA in question is a Spartan-3E, and we have not yet decided
    > upon the exact package yet.
    >
    > If this task is not feasible in VHDL alone, what external RAM device
    > might be recommended? Having the VHDL for access to such an external
    > RAM available for reference would be a big boon here.
    >
    > A side note on how this memory block will be used. One "task" will be
    > iterating over the block repeatedly, with data trickling in replacing
    > old values -- so each incoming byte stored in the RAM will be accessed
    > many times before it is overwritten.
    >
    > Any tips or links to materials regarding this would be greatly
    > appreciated.
    >
    > Thank you.
    >
    > Alex McHale
     
    Ricardo, Jul 5, 2006
    #6
  7. Alex

    Ray Andraka Guest

    radarman wrote:

    >
    > If you want to do it all internally, the only part big enough is the
    > XC3S1600E. However, you could simply plop on an external SRAM, have
    > enough RAM left over for growth, and get by with a MUCH smaller FPGA.
    > Even better would be an appropriately sized external dual-port RAM.
    > This would allow you to just implement your control logic and data
    > interface in the FPGA, which (depending on your application) could be a
    > much smaller device.
    >
    > FPGA's make for some very expensive RAM. If you need RAM in bulk, it's
    > generally better to just add RAM unless you have some other constraint
    > that forbids it.
    >


    I think you'll find that dual port RAM makes the FPGA look cheap. Dual
    port RAM devices are not generally commodity items, and the ones that
    are out there tend to dissappear into no longer available land pretty
    quickly. Since you already have the FPGA in the system, use the FPGA as
    an interface to a standard single ported RAM and time-multiplex the
    access. You'll need 2x the RAM bandwidth, so if you are limited in the
    clock period, double the width of the memory to make up for the slower
    time-multiplexed access. Use a few of the dual ported BRAMs in the FPGA
    to buffer data into and out of the SRAM and for clock domain crossings.
     
    Ray Andraka, Jul 5, 2006
    #7
  8. Alex

    Alex Guest

    Thanks to everyone who has replied.

    Can anyone point me to a good resource on learning to interface the
    FPGA with a RAM chip? I'm using VHDL for everything in the FPGA. The
    more example VHDL I can see, the better.

    This is a project that landed in my lap that I'm having to learn a lot
    for as I go. The more resources I have to learn how to use this FPGA
    and VHDL, the better.

    Thank you.

    Alex McHale
     
    Alex, Jul 5, 2006
    #8
  9. Alex

    Ricardo Guest

    The FPGA and RAM datasheet are very good starting points. The
    interface, well, the IO pins are there just for that purpouse.

    You may try google, opencores, hamburg hdl archive...

    Regards,


    Alex escreveu:

    > Thanks to everyone who has replied.
    >
    > Can anyone point me to a good resource on learning to interface the
    > FPGA with a RAM chip? I'm using VHDL for everything in the FPGA. The
    > more example VHDL I can see, the better.
    >
    > This is a project that landed in my lap that I'm having to learn a lot
    > for as I go. The more resources I have to learn how to use this FPGA
    > and VHDL, the better.
    >
    > Thank you.
    >
    > Alex McHale
     
    Ricardo, Jul 6, 2006
    #9
  10. Alex

    Nico Coesel Guest

    "Alex" <> wrote:

    >Thanks to everyone who has replied.
    >
    >Can anyone point me to a good resource on learning to interface the
    >FPGA with a RAM chip? I'm using VHDL for everything in the FPGA. The
    >more example VHDL I can see, the better.
    >
    >This is a project that landed in my lap that I'm having to learn a lot
    >for as I go. The more resources I have to learn how to use this FPGA
    >and VHDL, the better.


    This may be a good start:
    http://minila.sourceforge.net

    --
    Reply to nico@nctdevpuntnl (punt=.)
    Bedrijven en winkels vindt U op www.adresboekje.nl
     
    Nico Coesel, Jul 6, 2006
    #10
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