Mapping entity and components

Discussion in 'VHDL' started by Jan, Oct 17, 2008.

  1. Jan

    Jan Guest

    Dear all,

    I have the following VHDL which gives me some problems.

    entity pixel_bufferX3 is
    Port (
    R_0 : in STD_LOGIC_VECTOR (7 downto 0);
    G_0 : in STD_LOGIC_VECTOR (7 downto 0);
    B_0 : in STD_LOGIC_VECTOR (7 downto 0);
    R_1 : in STD_LOGIC_VECTOR (7 downto 0);
    G_1 : in STD_LOGIC_VECTOR (7 downto 0);
    B_1 : in STD_LOGIC_VECTOR (7 downto 0);
    R_2 : in STD_LOGIC_VECTOR (7 downto 0);
    G_2 : in STD_LOGIC_VECTOR (7 downto 0);
    B_2 : in STD_LOGIC_VECTOR (7 downto 0));
    end pixel_bufferX3;

    architecture Behavioral of pixel_bufferX3 is

    component BLOCKRAM512x72
    port (
    dina: IN std_logic_VECTOR(71 downto 0);
    end component;

    begin
    dp_pixbuf : BLOCKRAM512x72
    port map (
    dina => R_0(7 downto 0) & G_0(7 downto 0),
    );


    end Behavioral;

    I'm trying to map all the inputs from the entity to one large bus and
    map it to the dina. How to do that? Am I forced to make a local signal
    and first map the inputs to that and then map dina with it?

    Thank you in advance!

    Regards
    Jan
     
    Jan, Oct 17, 2008
    #1
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  2. Jan

    Tricky Guest

    On 17 Oct, 15:58, Jan <webpjat@future-design_DELETE.dk> wrote:
    > Dear all,
    >
    > I have the following VHDL which gives me some problems.
    >
    > entity pixel_bufferX3 is
    >      Port (
    >             R_0 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             G_0 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             B_0 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             R_1 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             G_1 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             B_1 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             R_2 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             G_2 : in  STD_LOGIC_VECTOR (7 downto 0);
    >             B_2 : in  STD_LOGIC_VECTOR (7 downto 0));
    > end pixel_bufferX3;
    >
    > architecture Behavioral of pixel_bufferX3 is
    >
    > component BLOCKRAM512x72
    >         port (
    >         dina: IN std_logic_VECTOR(71 downto 0);
    > end component;
    >
    > begin
    >         dp_pixbuf : BLOCKRAM512x72
    >                 port map (
    >                         dina => R_0(7 downto 0) & G_0(7 downto 0),
    >                 );
    >
    > end Behavioral;
    >
    > I'm trying to map all the inputs from the entity to one large bus and
    > map it to the dina. How to do that? Am I forced to make a local signal
    > and first map the inputs to that and then map dina with it?
    >
    > Thank you in advance!
    >
    > Regards
    >    Jan


    You have to do the latter, ie. make a temporary signal that's as long
    as dina and connect to to dina. Only type conversions are allowed on
    port maps.

    Im sure in the new VHDL spec, the first method will be allowed.
     
    Tricky, Oct 17, 2008
    #2
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  3. Jan

    none Guest

    Jan wrote:
    > Dear all,
    >
    > I have the following VHDL which gives me some problems.
    >
    > entity pixel_bufferX3 is
    > Port (
    > R_0 : in STD_LOGIC_VECTOR (7 downto 0);
    > G_0 : in STD_LOGIC_VECTOR (7 downto 0);
    > B_0 : in STD_LOGIC_VECTOR (7 downto 0);
    > R_1 : in STD_LOGIC_VECTOR (7 downto 0);
    > G_1 : in STD_LOGIC_VECTOR (7 downto 0);
    > B_1 : in STD_LOGIC_VECTOR (7 downto 0);
    > R_2 : in STD_LOGIC_VECTOR (7 downto 0);
    > G_2 : in STD_LOGIC_VECTOR (7 downto 0);
    > B_2 : in STD_LOGIC_VECTOR (7 downto 0));
    > end pixel_bufferX3;
    >
    > architecture Behavioral of pixel_bufferX3 is
    >
    > component BLOCKRAM512x72
    > port (
    > dina: IN std_logic_VECTOR(71 downto 0);
    > end component;
    >
    > begin
    > dp_pixbuf : BLOCKRAM512x72
    > port map (
    > dina => R_0(7 downto 0) & G_0(7 downto 0),
    > );
    >
    >
    > end Behavioral;
    >
    > I'm trying to map all the inputs from the entity to one large bus and
    > map it to the dina. How to do that? Am I forced to make a local signal
    > and first map the inputs to that and then map dina with it?
    >
    > Thank you in advance!
    >
    > Regards
    > Jan


    How about doing this?

    dp_pixbuf : BLOCKRAM512x72
    port map (
    dina(71 downto 64) => R_0(7 downto 0)
    dina(63 downto 56) => G_0(7 downto 0),
    );

    and so on..

    Ron
     
    none, Oct 17, 2008
    #3
  4. Jan

    Jan Guest

    none wrote:
    > Jan wrote:


    > How about doing this?
    >
    > dp_pixbuf : BLOCKRAM512x72
    > port map (
    > dina(71 downto 64) => R_0(7 downto 0)
    > dina(63 downto 56) => G_0(7 downto 0),
    > );
    > and so on..
    > Ron

    I just tried it, and the syntax does not work. I get the following error
    "An index or element of the formal port dina of BLOCKRAM512x72 is
    missing in instantiation."
    But it works with using the local signal.

    Regards
    Jan
     
    Jan, Oct 17, 2008
    #4
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