message no data on modelsim

Discussion in 'VHDL' started by picnanard, Mar 12, 2007.

  1. picnanard

    picnanard

    Joined:
    Mar 5, 2007
    Messages:
    19
    Hello,

    I have design with several layer.
    (component consist of components)
    I use a vhdl file bench for test my design with modelsim
    No problem when i see the signal declared on the bench
    i can see them.
    But when i want look signal declared inside the design i can't.
    On the istance windows modelsim i choose a signal
    and i add it (add to wave) and near the signal appear -No signal-
    This massage appear on all signal declared inside the design!
    When can i look them??

    i hope to be clear
     
    picnanard, Mar 12, 2007
    #1
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