Multi-source

Discussion in 'VHDL' started by Roya, Aug 20, 2009.

  1. Roya

    Roya

    Joined:
    Jun 30, 2009
    Messages:
    4
    hi, every one
    i have problem in my design. I use 2 signals :eek:ne for hand-shake and one for acknowledgment . in the process1 the hand_shake signal should be one and the ACK signal should be zero, on the other hand in the process2 all should be inverted ,means:hand_shake signal should be zero and ACK signal should be one. Actualy each process provides true condition for another process.

    also, these signals are used in the conditional statment (if-else) at both processes.

    process1
    if(H_S='1' and ACK='0') then
    ....
    .
    .
    H_S<='0';
    ACK<='1';
    end process1;

    process2
    if(H_S='0' and ACK='1') then
    ....
    .
    .
    H_S<='1';
    ACK<='0';
    end process2;

    so this concept is wrong because the two processes assigned values to these signals mutually so multi-source happens .
    as U see i realy need this concept, how can i make it true although it carry my concept?!
    I appreciate so much if someone help me. Thank U so much :)
     
    Roya, Aug 20, 2009
    #1
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  2. Roya

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi
    This one the classic problems to concider while writing VHDL code.
    If you where writing code in C++ or Java would it be Ok to acess the same variable from two different functions.
    But VHDL code for synthesizing will in the end be hardware and you can't just connect two output directly.
    (or control the same output from two concurrent processes)

    The solution: 1) Use only process to control a signal - they seems to be close related anyway
    2) Implement an external multiplexer to select among the two signals like this..
    ACK <= ACK1 when Select='0' else ACK2;

    Hope it helped you
     
    Last edited: Aug 22, 2009
    jeppe, Aug 22, 2009
    #2
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