Need some help!

Discussion in 'VHDL' started by bhiggins@umr.edu, Apr 9, 2005.

  1. Guest

    Why am I getting this error:

    ERROR:Xst:528 - Multi-source in Unit <waittime> on signal <z>
    Sources are:
    Signal <z> in Unit <waittime> is assigned to GND
    ERROR:Xst:415 - Synthesis failed
    CPU : 1.72 / 2.52 s | Elapsed : 2.00 / 3.00 s

    I have a very simple schematic with waittime going out to an output
    marker.

    waittime:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    -- Uncomment the following lines to use the declarations that are
    -- provided for instantiating Xilinx primitive components.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity waittime is
    Port ( z : out std_logic);
    end waittime;

    architecture Behavioral of waittime is

    begin
    z <= '1' after 500000000 ns;

    z <= '0' after 500000000 ns;

    end Behavioral;


    I am using a CR-II c256 and ISE 6.3.03i.

    Any help would be appreciated!

    Thanks,
    Brian
    , Apr 9, 2005
    #1
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  2. fpgawizz Guest

    Brian
    Looks like your code is meant for simulation purposes. And you have 2
    concurrent signal assignment statements on "z" which is z <= '1' follwed
    by z <= '0'. thats why you are getting the multisource error.
    Doing something like z <= not z after 50 ns woulg give you a toggling
    signal "z". Make sure you initialize "z" to '0'. After clauses are for sim
    purposes only. I am assuming you are just doing a simulation here.
    fpgawizz, Apr 9, 2005
    #2
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  3. Guest

    I am actually wanting the cpld to toggle the signal for real not for
    just simulation. What should I use instead of "after"? How should I
    toggle it so I do not get the multisource error?

    Thanks in advance,
    Brian
    , Apr 9, 2005
    #3
  4. fpgawizz Guest

    You have to use a clock to do your toggling. You can have two states in a
    state machine where in state 1, you set z to 0, and in state 2 z is set
    to 1 and this state machine is clocked by your 50 ns clock. z would then
    be a toggling signal.
    fpgawizz, Apr 9, 2005
    #4
  5. wrote:

    > ERROR:Xst:528 - Multi-source in Unit <waittime> on signal <z>


    You are driving a value to one signal from more than one process. (Note
    that every concurrent statement ist also considered as a process.)


    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;


    Just a note: It is not recommended to used these libraries, as their
    implementation dependts on the simulator / synthesizer. Use
    IEEE.Numeric_std.ALL instead.



    >
    > begin
    > z <= '1' after 500000000 ns;
    >
    > z <= '0' after 500000000 ns;
    >
    > end Behavioral;


    Two concurrent statements driving z.

    process -- no sensitivity list - triggered at simulation start
    begin
    z <= '1' after 500000000 ns;
    z <= '0' after 500000000 ns;
    wait; -- uncomment to execute the process again after end
    end process;


    Note: This is only for simulation. the after-clause is NOT synthesizable.

    Whats your intention for this piece of code? Is it a clock or just a
    signal, that should be high and go to low later.
    If it is a clock - take an internal clock generator from you FPGA or use
    the clock via a FPGA input pin.
    I it is a signal - you need a clock with a period suitable for you
    desired "delays". Test e.g. for the rising_edge(clock).

    Ralf
    Ralf Hildebrandt, Apr 9, 2005
    #5
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