I just started working on my first real VHDL project. I need to find a way to get a signal that will look like this ------__---__------ The negative pulses are 60 ns, with 20 ns in between them. I tried WAIT and AFTER statements but I can't seem to get anything to work correctly. I have a 20ns clock. Also, the pulses have to go negative after another signal(busy) goes goes neg.
Thanks,
c130herc
Thanks,
c130herc