(newbie) 2 read/write register

Discussion in 'VHDL' started by Max, Sep 4, 2003.

  1. Max

    Max Guest

    I have two read/write register; each one has its chip-enable, thane
    there are data bus, and read/write signals.

    I wrote the following code, and seems to work:
    ----------------8<---------------------
    entity reg_rw is
    Port ( rd : in std_logic;
    wr : in std_logic;
    ce0 : in std_logic;
    ce1 : in std_logic;
    reset : in std_logic;
    db : inout std_logic);
    end reg_rw;

    architecture Behavioral of reg_rw is

    signal data0,data1: std_logic;

    begin

    --- write 0
    write0: process (reset, ce0, wr)
    begin
    if reset = '1' then
    data0 <= '0';
    elsif ce0 = '1' then
    if rising_edge(wr) then
    data0 <= db;
    end if;
    end if;
    end process;
    -------------

    --- write 1
    write1: process (reset, ce1, wr)
    begin
    if reset = '1' then
    data1 <= '0';
    elsif ce1 = '1' then
    if rising_edge(wr) then
    data1 <= db;
    end if;
    end if;
    end process;
    ------------

    --- read global
    read_global: process (ce0, ce1, rd)
    begin
    if ce1 = '0' and ce0 = '0' then
    db = 'Z';
    elsif rd = '1' then
    if ce1 = '1' then
    db <= data1;
    elsif ce0 = '1' then
    db <= data0;
    end if;
    end if;
    end process;
    --------------

    end Behavioral;
    --------------8<-----------------------

    There is another way to do the same thing? For examble I would like to
    put all code regarding a register in a single process, so how can I
    write a process to read/write one register (the processes would be
    "read_write0" and "read_write1")?
    If it is not possible to put both read and write inside a sigle
    process, then I would like to split read: how can I write two process
    that each read only one register (4 processes: read0, write0, read1
    and write1)?


    thanks
    Max, Sep 4, 2003
    #1
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  2. Max

    eadgbe Guest

    You need to get into the habit, right now, of using just clock and reset in your sensitivity list.

    process(reset,clk)
    begin
    if reset = '1' then
    data0 <= '0';
    data1 <= '0';
    elsif rising_edge(clk) then
    if ce0 = '1' then
    data0 <= db;
    end if;
    if ce1 = '1' then
    data1 <= db;
    end if;
    end if;
    end process;

    That's the proper way to do an enabled register. Don't try to wrap the clock inside
    the enable. You can call your clock "wr"....whatever. But think of it as a clock and
    keep your design synchronous.

    As for the read....thats just a mux. Do it in a concurrent statement.

    db <= 'z' when rd = '0' else
    data0 when ce0 = '1' else
    data1;

    And you have to make damned sure that wr and rd aren't high at the same time or you are going
    to trap what you are reading out.

    Bob


    "Max" <> wrote in message news:...
    > I have two read/write register; each one has its chip-enable, thane
    > there are data bus, and read/write signals.
    >
    > I wrote the following code, and seems to work:
    > ----------------8<---------------------
    > entity reg_rw is
    > Port ( rd : in std_logic;
    > wr : in std_logic;
    > ce0 : in std_logic;
    > ce1 : in std_logic;
    > reset : in std_logic;
    > db : inout std_logic);
    > end reg_rw;
    >
    > architecture Behavioral of reg_rw is
    >
    > signal data0,data1: std_logic;
    >
    > begin
    >
    > --- write 0
    > write0: process (reset, ce0, wr)
    > begin
    > if reset = '1' then
    > data0 <= '0';
    > elsif ce0 = '1' then
    > if rising_edge(wr) then
    > data0 <= db;
    > end if;
    > end if;
    > end process;
    > -------------
    >
    > --- write 1
    > write1: process (reset, ce1, wr)
    > begin
    > if reset = '1' then
    > data1 <= '0';
    > elsif ce1 = '1' then
    > if rising_edge(wr) then
    > data1 <= db;
    > end if;
    > end if;
    > end process;
    > ------------
    >
    > --- read global
    > read_global: process (ce0, ce1, rd)
    > begin
    > if ce1 = '0' and ce0 = '0' then
    > db = 'Z';
    > elsif rd = '1' then
    > if ce1 = '1' then
    > db <= data1;
    > elsif ce0 = '1' then
    > db <= data0;
    > end if;
    > end if;
    > end process;
    > --------------
    >
    > end Behavioral;
    > --------------8<-----------------------
    >
    > There is another way to do the same thing? For examble I would like to
    > put all code regarding a register in a single process, so how can I
    > write a process to read/write one register (the processes would be
    > "read_write0" and "read_write1")?
    > If it is not possible to put both read and write inside a sigle
    > process, then I would like to split read: how can I write two process
    > that each read only one register (4 processes: read0, write0, read1
    > and write1)?
    >
    >
    > thanks
    eadgbe, Sep 4, 2003
    #2
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