Not used inputs - what to do with it

Discussion in 'VHDL' started by MJ, Dec 17, 2007.

  1. MJ

    MJ Guest

    Hello,

    I have some unused bits of a bit vector in my entity.
    This bit vector is the data bus and I do not use all bits of this bus.

    Here is a example what I want to do:

    entity top is
    Port ( clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    we_n: in STD_LOGIC;
    output : out STD_LOGIC_VECTOR (23 downto 0);
    data : in STD_LOGIC_VECTOR (31 downto 0));
    end top;
    architecture Behavioral of top is

    signal timing_in : std_logic_vector(23 downto 0);

    begin
    timing_in(2 downto 0) <= data(2 downto 0);
    timing_in(5 downto 3) <= data(6 downto 4);
    timing_in(8 downto 6) <= data(10 downto 8);
    timing_in(11 downto 9) <= data(14 downto 12);
    timing_in(14 downto 12) <= data(18 downto 16);
    timing_in(17 downto 15) <= data(22 downto 20);
    timing_in(20 downto 18) <= data(26 downto 24);
    timing_in(23 downto 21) <= data(30 downto 28);

    PROCESS(clk, rst)
    BEGIN
    IF rst = '1' then
    output <= (others => '0');
    ELSIF (clk'EVENT AND clk = '1') THEN
    IF(we_n = '0') THEN
    output <= timing_in;
    END IF;
    END IF;
    END PROCESS;

    end Behavioral;

    What can I do to avoid warnings that the input signal data(3),
    data(7) ... is not used?
    Of cours I can split the bus in elements in the entity but I do not
    like this solution.
    If there Is a known discussion about this issue? Then a link would be
    helpful.

    Thanks for your help.

    Markus Jank
    MJ, Dec 17, 2007
    #1
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  2. MJ

    Symon Guest

    "MJ" <> wrote in message
    news:...
    > Hello,
    >
    > I have some unused bits of a bit vector in my entity.
    > This bit vector is the data bus and I do not use all bits of this bus.
    >
    > What can I do to avoid warnings that the input signal data(3),
    > data(7) ... is not used?
    >
    > Thanks for your help.
    >

    Hi Markus,
    Just ignore them? A lot of synthesis/simulation tools nowadays let you block
    warnings you don't care about.
    HTH., Syms.
    Symon, Dec 17, 2007
    #2
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  3. MJ wrote:

    > What can I do to avoid warnings that the input signal data(3),
    > data(7) ... is not used?


    It's a valid warning. Ignore it or fix it.
    I would eliminate the "data" signal and
    make "timing_in" an input port matching "output" exactly,
    and do the data slicing in the port map.

    -- Mike Treseler
    Mike Treseler, Dec 17, 2007
    #3
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