If the target device does not support initial values then that would be the
correct behaviour of the tool. If the target device does support a power up
value for registers than I still say that the service request should be
opened to the supplier for non-compliance to the VHDL standard.
But that doesn't sound like a 'tool' thing, it sounds like a way to make the
code re-usable when targeted towards devices that either do or not support
power up defined values. I thought your point had to do with grumblings
about synthesis tools but it appears that it really has to do with physical
parts that do not have guaranteed power up values.
KJ
The most often confused part about reset and initial conditions (in
FPGA's, where reliable initial conditions are possible), is that
neither handles the transition from reset or configuration to normal
operation automatically and correctly. However, an explicit reset
gives the user more options to correctly implement the transition.
For example, a counter is initialized/reset to zero, but on the first
clock out of reset (or configuration), the counter counts down,
resulting in a rollover. Unless the reset or end of configuration is
synchronized to the clock, the entire contents of the counter become
undefined. And this problem is not just related to counters. One-hot
state machines can get into illegal states if transitions are allowed
on the first clock out of reset/configuration. In the old days (before
FPGA's and dirt), we used to have rules about down counters being
initialized to odd values, and up counters initialized to even values,
initial transitions on state machines being single bit transitions,
etc. to combat this. These methods are still valid, but are much less
reviewable/auditable/verifiable that correctly handling the timing
relationship between the clock and the end of configuration or reset.
This timing relationship can be handled by traditionally synchronizing
the deassertion of reset, or by delaying the clock sufficiently after
the deassertion of reset/config. The latter is applicable regardless
of whether reset is explicitly coded; the former is applicable only to
explicit resets.
Some FPGA storage elements (e.g. RAM) do not have a reset capability,
but do have an initialization (via configuration) capability. It is
vital that either the clock be disabled sufficiently after
configuration is complete, or that the contents of the ram are not
allowed to change on the first clock after configuration is complete
(assuming one clock period is long enough to guarantee that all
storage elements are out of configuration).
In summary, just because VHDL initial conditions are supported by a
synthesis tool does not mean that all initialization problems are
automatically handled by them.
Andy
