Onchip SRAM Vs Registers

Discussion in 'VHDL' started by john.deepu@gmail.com, Mar 25, 2005.

  1. Guest

    Hi all,
    Can anyone tell me what is the threshold point(memory size) to opt
    for Onchip SRAM instead of FlipFlops , considering the Power&Area. In a
    module I have ~5Kbit of memory implemented as verilog registers. I
    would like to know the Power/Area savings if I switch to SRAM instead
    of Flipflops. I use .13u process.
    Any links/documents in this regard are highly welcome.
    Thanks
    Deepu John
     
    , Mar 25, 2005
    #1
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  2. Peter Alfke Guest

    John, your question seems to relate to ASIC design. This newsgroup
    deals with FPGAs where you select and then use a given architecture.
    That means the trade-offs are different.
    Modern FPGAs have SRAM blocks of various sizes, from 512 bits to 18 k
    bits and even larger. Xilinx offers the RAM option in the Look-up
    Tables (LUTs), which can even be used as shift registers.
    The designer's decision is to use available resources, not to design
    latches or flip-flops.
    This can lead to peculiar design optimizations when a certain resource
    is abundant and not all used, e.g. BlockRAMs.
    5k bit fits very comfortably in one 18 kbit dual-ported BlockRAM, but
    would take an inordinate amount of LUTs, even at 16 bits per LUT. You
    decide.
    Peter Alfke, Xilinx
     
    Peter Alfke, Mar 25, 2005
    #2
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