packages and hierarchy

[lablasa]

Hi!
I've a problem with similar packages in different libraries.
I mean, I've a library (proj_A) with its package (pkg_A) where I've declared array type
(type a_32bit is array (natural range <>) of std_logic_vector(31 downto 0))
Then I've instantiated this lib (whose ports are array types) in another lib (proj_B) which contains a pkg (pkg_B) with the same array types.
I've no problems if I compile proj_B in HDL Designer, but I have some errors when I try to simulate it in modelsim (Failure: (vsim-3807) Types do not match between component and entity for port "input").
I've already checked if the types are different but they aren't! They both are a_32bit.
Could anyone help me!?
Thanks!
lablasa

 

[lablasa]

Maybe my problem is not so clear...
I'm working with 2 libraries (proj_A and proj_B, each library has its own package (pkg_A and pkg_B) since each library should be synthetisizable as a "standalone library".
These packages are similar (both declare array types:
type a_2bit is array (natural range <>) of std_logic_vector(1 downto 0);
type a_8bit is array (natural range <>) of std_logic_vector(7 downto 0);
type a_32bit is array (natural range <>) of std_logic_vector(31 downto 0);
and so on...) and I need both.
When I instantiate proj_A in proj_B, I declare pkg_B only:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

LIBRARY proj_B;
USE proj_B.pkg_B.ALL;

LIBRARY proj_A;

entity ent_proj_B is
....
end ent_proj_B;

architecture struct of ent_proj_B is
...
component ent_proj_A
port....
end component;
.....
end struct;

The ports of proj_A are arrays, declared both in pkg_A and pkg_B but modelsim reports
Failure: (vsim-3807) Types do not match between component and entity for port "xxx"

I'm trying to understand if it's just a configuration problem, something concernig with the tools I'm using or, simply, I can't use array types as ports in different libraries...
Thanks,
lablasa.