P
Peter Soerensen
I have used VHDL for many years now.
I believe I have a good overview over existing packages.
I think two essential packages are missing:
I will call them BIT_LOGIC and STRING.
Can anyone explain why they have not been made long ago?
STRING (simulation only)
The standard TEXTIO is very primite and simple string functions that can
convert any signal type to a string for write to std_out are missing.
I have made my own and could not do any serious testbench and simulation
work without it. But I simply do not understand why the VHDL committee
has not made a standard lib.
I would propose something like the printf functions in C.
I know it is very easy to do, when you have tryed it ones, but it is a
large step for beginners and it is a vaste or resources that we all do it.
You can get my simple lib for a start, but is very primitive compared to
the printf statement. Anyone with a SW+VHDL background got do it better
than me within a very short time.
So why use bit when we have std_logic, this may be the reason.
First properly implement bit functions should be faster to simulate than
std_logic bacause they only have 2 values compare to 9.
Okay computers are fast and this is not the major reason for slow
simulation on big designs.
But second when designs logic without any tristate function like
internal signals in FPGA and must ASIC I find it much more logical to
use bits.
BIT_LOGIC
Originally VHDL was made without packages for synthesis because it was
made for simulation only. Later when synopsis started to support
synthesis and made the synopsys packages that support std_logic but to
day I would recommend these and only use VHDL standard libs: numeric_std
and numeric_bit. However no libs support a number of functions for bits
that exits in std_logic_1164; E.g:
function "not" (1:bit) return bit;
function "and" (1,r:bit) return bit;
etc
numeric_std defines logic for unsigned and even the rising_edge(clk) but
I miss the logic functions for bit and bit_vector when you do not need
or want to see them as numeric.
I believe I have a good overview over existing packages.
I think two essential packages are missing:
I will call them BIT_LOGIC and STRING.
Can anyone explain why they have not been made long ago?
STRING (simulation only)
The standard TEXTIO is very primite and simple string functions that can
convert any signal type to a string for write to std_out are missing.
I have made my own and could not do any serious testbench and simulation
work without it. But I simply do not understand why the VHDL committee
has not made a standard lib.
I would propose something like the printf functions in C.
I know it is very easy to do, when you have tryed it ones, but it is a
large step for beginners and it is a vaste or resources that we all do it.
You can get my simple lib for a start, but is very primitive compared to
the printf statement. Anyone with a SW+VHDL background got do it better
than me within a very short time.
So why use bit when we have std_logic, this may be the reason.
First properly implement bit functions should be faster to simulate than
std_logic bacause they only have 2 values compare to 9.
Okay computers are fast and this is not the major reason for slow
simulation on big designs.
But second when designs logic without any tristate function like
internal signals in FPGA and must ASIC I find it much more logical to
use bits.
BIT_LOGIC
Originally VHDL was made without packages for synthesis because it was
made for simulation only. Later when synopsis started to support
synthesis and made the synopsys packages that support std_logic but to
day I would recommend these and only use VHDL standard libs: numeric_std
and numeric_bit. However no libs support a number of functions for bits
that exits in std_logic_1164; E.g:
function "not" (1:bit) return bit;
function "and" (1,r:bit) return bit;
etc
numeric_std defines logic for unsigned and even the rising_edge(clk) but
I miss the logic functions for bit and bit_vector when you do not need
or want to see them as numeric.