Post Synthesis, Post PAR, and real hardware behavior?

Discussion in 'VHDL' started by scott.yuan523@gmail.com, Apr 25, 2007.

  1. Guest

    Hi all,

    I just started in VHDL. I wrote the code and performed a functional
    simulation (pre-synthesis). Output is what I expected. Performed a
    post synthesis simulation, obtained similar results. Then the post
    place-and-route (PAR) simulation gave me 'X' (don't care?) as part of
    the output.

    I then programed the device and the output is what I saw in the
    functional and post synthesis simulation results.

    My question is, what's the difference between these simulation models
    (post synthesis and post PAR)? Given that the post PAR simulation
    model is closest to hardware, how come the result is different from
    the actual output?

    Thanks in advance!
    , Apr 25, 2007
    #1
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  2. wrote:

    > My question is, what's the difference between these simulation models
    > (post synthesis and post PAR)? Given that the post PAR simulation
    > model is closest to hardware, how come the result is different from
    > the actual output?


    This is most likely a bug in the testbench
    reset/clock synchronization, not the synthesis code.
    If you pass static timing and it
    works on the bench, I wouldn't
    spend much time on it.

    -- Mike Treseler
    Mike Treseler, Apr 25, 2007
    #2
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  3. On 25 Apr., 19:03, wrote:
    > I just started in VHDL. I wrote the code and performed a functional
    > simulation (pre-synthesis). Output is what I expected. Performed a
    > post synthesis simulation, obtained similar results. Then the post
    > place-and-route (PAR) simulation gave me 'X' (don't care?) as part of
    > the output.


    Don't care is '-', 'X' means unknown. A X can be obtained by two
    driver on the same signal, but also if there is no driver for a signal
    or if your library throws 'X' after setup/hold violations.
    A 'X' is not necessarily an error, but something you need to inspect
    carefully.

    bye Thomas
    Thomas Stanka, Apr 26, 2007
    #3
  4. Guest

    Thanks for the responses!

    On Apr 26, 4:11 am, Thomas Stanka <> wrote:
    > Don't care is '-', 'X' means unknown. A X can be obtained by two
    > driver on the same signal, but also if there is no driver for a signal
    > or if your library throws 'X' after setup/hold violations.
    > A 'X' is not necessarily an error, but something you need to inspect
    > carefully.
    >
    > bye Thomas


    I looked at both the RTL and technology schematic. There's only one
    driver for the output.
    , Apr 26, 2007
    #4
  5. Andy Guest

    On Apr 26, 3:11 am, Thomas Stanka <> wrote:
    > On 25 Apr., 19:03, wrote:
    >
    > > I just started in VHDL. I wrote the code and performed a functional
    > > simulation (pre-synthesis). Output is what I expected. Performed a
    > > post synthesis simulation, obtained similar results. Then the post
    > > place-and-route (PAR) simulation gave me 'X' (don't care?) as part of
    > > the output.

    >
    > Don't care is '-', 'X' means unknown. A X can be obtained by two
    > driver on the same signal, but also if there is no driver for a signal
    > or if your library throws 'X' after setup/hold violations.
    > A 'X' is not necessarily an error, but something you need to inspect
    > carefully.
    >
    > bye Thomas


    Typically the result of no driver for a std_logic signal is a
    'U' (uninitialized), rather than an 'X', unless there is an explicit
    initializer in the signal declaration.

    Andy
    Andy, Apr 26, 2007
    #5
  6. On 26 Apr., 19:37, Andy <> wrote:
    > > Don't care is '-', 'X' means unknown. A X can be obtained by two
    > > driver on the same signal, but also if there is no driver for a signal
    > > or if your library throws 'X' after setup/hold violations.
    > > A 'X' is not necessarily an error, but something you need to inspect
    > > carefully.

    >
    > Typically the result of no driver for a std_logic signal is a
    > 'U' (uninitialized), rather than an 'X', unless there is an explicit
    > initializer in the signal declaration.


    You are right, I was a bit fast. A signal with no driver is a U in
    first place. I thought about GTL-gates driving X when having no driver
    (U at an Input). I see this sometimes especially when using Verilog
    library elements.

    bye Thomas
    Thomas Stanka, Apr 27, 2007
    #6
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