Peppe said:
If the results should be same...why should I do both simulation?
Because the results 'should be' the same....and 'should be' does not imply
'must be'. If you're skilled in use of the language you will already have
the knowledge to avoid the constructs that are problematic to implement or
which can cause problems.....but that doesn't mean that you can't
inadvertantly create those things.
If you're doing ASIC designs you are generally required to complete
post-synthesis simulation before signoff because the costs of being wrong
are rather large.
In most FPGA applications by a skilled designer, post-synthesis simulation
would only be done at the tail end of the design cycle once you're fairly
sure that the design is stable. It should not be done as part of the normal
'design/debug' cycle simply because using the post-synthesis model runs much
slower (since it much more detailed since it maps relatively closely to the
actual physical implementation).
If you're somewhat less skilled (or supervising someone you're not certain
of their skill level) you might want to have post-synthesis simulations
completed as just another check that the design is correct since even in the
FPGA world, debug and finding problems on hardware are more expensive than
during simulation.
KJ