Power consumption estimation

Discussion in 'VHDL' started by AG, Mar 9, 2006.

  1. AG

    AG Guest

    Hi,

    I have a design with two identical 16 taps filters runing in parallel on the
    same inputs.
    A switch allow to disable one of the two filters.

    I also have two test bench runing on the same inputs :
    - one has the two filters enabled.
    - one has only one filter enabled.

    I used post-synthesis files (.vho) to simulate the two test bench and record
    all signals into .vcd files (values changed dump files)

    I use these .vcd files to perform Power consumption estimation for the two
    test bench.

    In the case where only one filter is running, I only have 45% of the nodes
    toggled during simulation.
    In the case where the two filters are running, I get 85% of the nodes
    toggled during simulation.

    In the first case, the powerplay power analyser inidcates a low power
    estimation confidence.
    In the second case, the powerplay power analyser indicates a medium power
    estimation confidence.

    Can I consider the power estimation confidence in the first case medium as
    in the second case, knowing that if the estimation is low, it's just because
    I have intentionally not used half (1 filter out of 2) of the design ?
     
    AG, Mar 9, 2006
    #1
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