VHDL assignment

Discussion in 'VHDL' started by shanawaz, Apr 23, 2009.

  1. shanawaz

    shanawaz

    Joined:
    Apr 18, 2009
    Messages:
    2
    1. Read and work through “VHDL Simulation example using VHDL Simili/Sonata”. Hand in the associated files (VHDL code and annotated simulation results) as part of your report. Do not make any changes to the code given in the handout.
    2. Modify the counter example from (1) so that data may be synchronously loaded into the counter. That is, write a VHDL model of a presettable counter – one which has data input lines and an active low “load” control. If the load control is low during the active clock edge the counter‟s outputs are made equal to the data on the data inputs. If you are unsure about the operation of presettable counters consult a textbook on logic design, or the data sheet of a suitable discrete logic device (e.g. from the 4000 series, 74xx series etc). All input and output signals must be std_logic or std_logic_vector.
    3. Write a high-level behavioural VHDL model of a 32-word by 8-bit memory in which the contents of the memory are initialised by reading from a text file (e.g. this idea could be used to model a ROM, or a RAM in which data has already written).
    The memory should have 4 address lines, 8 bi-directional, tristate data lines, and an active low enable input. When the enable is low the memory will read or write in accordance with the state of the read/write input. The read/write input is a single bit, 1 indicating read and 0 indicating write. The memory does not have a reset input. The memory does not have a clock. All input and output signals must be std_logic or std_logic_vector (i.e. not integers etc).
    Write a test bench for the memory which verifies the file has been read to initialise the memory and that write and subsequent read operations can be performed correctly.
    Hints: 1) make sure you know how to model bidirectional ports and signals having multiple sources (the data lines are driven by both the memory outputs and the testbench stimulus signals or other circuit models). The data lines should be high impedance („Z‟) when not in use for reading or writing, make sure that both you memory model and test bench adhere to this. 2) Use the IEEE TEXTIO package for file reading and writing functions matched to the IEEE data types.
    4. Write a test bench in which a counter is used to read out the contents of the memory (e.g. this idea could be used to model a program counter in a basic processor reading a program from memory). This testbench will contain a two-component netlist in which the counter from (1) or (2) is directly connected to the memory from (3). Do not write new architectures for the counter and memory and do not modify their interfaces (entity ports). The 4 bits from the counter should drive the least significant bits of the memory‟s address; the fifth address bit should remain 0 in this test.
    Please hand in VHDL source code (with comments!), and simulation output annotated with explanatory notes, together with relevant input files. Print out VHDL source and simulation results directly from the software, or as basic text files, or captured screenshots. Make sure that the code in you report uses a non-proportional font (such as Courier New) and that layout (indentation etc) is correct. Poor layout will loose marks. Annotate the simulations by writing on them by hand to indicate where significant things are happening in the simulation.
    Your work must contain sufficient comments and explanation to be easily comprehensible and must be coherently put together; however, a full formal report is not required. In particular background "theory" and general explanations of VHDL etc are not required. Although a standard formal report is not required, work which has insufficient comments or accompanying notes for it to be clear what you did and why (and to what extent it was successful) will receive few marks. Divide your report into four sections relating to the four tasks listed above.
    This must be your own work, although you are free to use public-domain examples for guidance. If your VHDL code is based on that given in textbooks, or other sources, you must full identify these sources in comments in your code. You will not lose marks for basing your work on such resources as long as they are correctly adapted to the above requirements, properly and fully implemented (simulated and evaluated) by you individually and the source is fully acknowledged. You must not base your work on that of other students or share code.
     

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    shanawaz, Apr 23, 2009
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  2. shanawaz

    JohnDuq

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    The first thing I would do is read the suggested material, and then do the work. If VHDL is not enjoyable, change majors now!

    John
     
    JohnDuq, Apr 23, 2009
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  3. shanawaz

    shanawaz

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    Apr 18, 2009
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    control unit

    hey guys ,

    will u explain me how this circuit diagram works , what is silence thereshold ?


    thanks in advance
     

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    shanawaz, Apr 26, 2009
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