Problems with DPLLing

Discussion in 'VHDL' started by MNQ, Jun 3, 2004.

  1. MNQ

    MNQ Guest

    Hi All

    I'm trying to write some code to synchronise my local clock with some
    incoming data. At the moment when the receiver sees a specific bit pattern,
    it makes pattern go to logic 1 for one clock period. This resets my clock
    and adds a small delay to my 2MHz clock. If I use this method I effectively
    loose a clock cycle which I cannot afford. I want to reset my clock on the
    rising edge of pattern, but when I use the code

    If pattern='1' and pattern'event then clock_divide<="00010" ;

    I get a bad synchronous error when I synthesize

    Am I correct in thinking that this is a digital phase locked loop?

    Can anyone suggest a way of doing this as I have no idea at the moment and
    time is slipping by.

    Thanks for any help


    clk = 65.536MHz
    clock_2MHz should be 2.048MHz
    CPLD is XC2C384

    clock_divider : PROCESS (clk, pattern)
    BEGIN
    IF pattern='1' THEN clock_divide <= "00010";
    ELSIF clk='1' AND clk'event THEN
    clock_divide <= clock_divide - 1;
    END IF;
    END PROCESS clock_divider;

    clock_2MHz <= clock_divide(4);


    --
    Mr Naveed Qayyum

    www.mnq.org.uk
    MNQ, Jun 3, 2004
    #1
    1. Advertising

  2. "MNQ" <> wrote in message news:<c9mr9a$5tv$>...
    > I want to reset my clock on the rising edge of pattern, but when I use the code If pattern='1' and pattern'event then clock_divide<="00010" ;
    > I get a bad synchronous error when I synthesize
    >


    Hi,

    Reset inputs on flipflops in FPGAs are level sensitive. You cant reset
    them on the edge. Use synchronous clear to avoid all trouble connected
    with asynchronous design.

    /Peter
    Peter Hermansson, Jun 3, 2004
    #2
    1. Advertising

  3. MNQ

    MNQ Guest

    Thanks for the advise but now I get the following

    ERROR:Xst:1534 - Sequential logic for node <clock_divide> appears to be
    controlled by multiple clocks.
    ERROR:Xst:739 - Failed to synthesize logic for signal <clock_divide>.
    ERROR:Xst:1431 - Failed to synthesize unit <tranceiver>.

    I changed the code to that shown below.

    Do you know what I am doing wrong?

    Thanks

    clock_divider : PROCESS (clk, pattern)
    BEGIN
    IF clk='1' AND clk'event THEN
    IF pattern'event THEN
    clock_divide <= "00000";
    else
    clock_divide <= clock_divide - 1;
    end if;
    END IF;
    END PROCESS clock_divider;

    --
    Mr Naveed Qayyum

    www.mnq.org.uk
    "Peter Hermansson" <> wrote in message
    news:...
    > "MNQ" <> wrote in message

    news:<c9mr9a$5tv$>...
    > > I want to reset my clock on the rising edge of pattern, but when I use

    the code If pattern='1' and pattern'event then clock_divide<="00010" ;
    > > I get a bad synchronous error when I synthesize
    > >

    >
    > Hi,
    >
    > Reset inputs on flipflops in FPGAs are level sensitive. You cant reset
    > them on the edge. Use synchronous clear to avoid all trouble connected
    > with asynchronous design.
    >
    > /Peter
    MNQ, Jun 3, 2004
    #3
  4. "MNQ" <> wrote in message news:<c9ne23$qb5$>...
    > Thanks for the advise but now I get the following
    >
    > ERROR:Xst:1534 - Sequential logic for node <clock_divide> appears to be
    > controlled by multiple clocks.
    > ERROR:Xst:739 - Failed to synthesize logic for signal <clock_divide>.
    > ERROR:Xst:1431 - Failed to synthesize unit <tranceiver>.
    >
    > I changed the code to that shown below.
    >
    > Do you know what I am doing wrong?
    >
    > Thanks
    >
    > clock_divider : PROCESS (clk, pattern)
    > BEGIN
    > IF clk='1' AND clk'event THEN
    > IF pattern'event THEN
    > clock_divide <= "00000";
    > else
    > clock_divide <= clock_divide - 1;
    > end if;
    > END IF;
    > END PROCESS clock_divider;
    >
    > --
    > Mr Naveed Qayyum


    Unless your CPLD allows multiple clock inputs for CLB flip flops, this
    will not work. Your flip flop has 2 clocks: clk and pattern, because
    you are using an event on either to change the flip flop. Furthermore
    any change in pattern (0 -> 1 or 1 -> 0) will be seen as a clock
    event, since you did not specify pattern = '1' or pattern = '0'.

    The code below would work better, assuming that clk is continuous. You
    can adjust the preset value of clock_divide to something other than
    "00000" to change the phase of the 2MHz clock. Note that clock_divide
    should also be in the sensitivity list.

    clock_divider : PROCESS (clk, pattern, clock_divide)
    BEGIN
    IF clk='1' AND clk'event THEN
    IF pattern = '1' THEN
    clock_divide <= "00000";
    else
    clock_divide <= clock_divide - 1;
    end if;
    END IF;
    END PROCESS clock_divider;

    However in your original post you said somehting about that when
    pattern = 1 it also resets your clock, i.e. clk -> 0. If this is so,
    then you are in bad shape as the above code will never work, since it
    requires clk = '1' and pattern = '1' at the same time. It seems like a
    bad design to me.
    Ralfe Cookson, Jun 4, 2004
    #4
  5. (Ralfe Cookson) wrote in message news:<>...
    > "MNQ" <> wrote in message news:<c9ne23$qb5$>...
    > Note that clock_divide
    > should also be in the sensitivity list.
    >
    > clock_divider : PROCESS (clk, pattern, clock_divide)
    > BEGIN
    > IF clk='1' AND clk'event THEN
    > IF pattern = '1' THEN
    > clock_divide <= "00000";
    > else
    > clock_divide <= clock_divide - 1;
    > end if;
    > END IF;
    > END PROCESS clock_divider;
    >



    I dont agree that pattern and clock_divide shall be in the sensitivity
    list.
    The generated hardware is only activated on rising edges on the clk
    signal, so clk shall be the only signal in the sensitivity list.

    /Peter
    Peter Hermansson, Jun 4, 2004
    #5
  6. (Peter Hermansson) wrote in message news:<>...
    > (Ralfe Cookson) wrote in message news:<>...
    > > "MNQ" <> wrote in message news:<c9ne23$qb5$>...
    > > Note that clock_divide
    > > should also be in the sensitivity list.
    > >
    > > clock_divider : PROCESS (clk, pattern, clock_divide)
    > > BEGIN
    > > IF clk='1' AND clk'event THEN
    > > IF pattern = '1' THEN
    > > clock_divide <= "00000";
    > > else
    > > clock_divide <= clock_divide - 1;
    > > end if;
    > > END IF;
    > > END PROCESS clock_divider;
    > >

    >
    >
    > I dont agree that pattern and clock_divide shall be in the sensitivity
    > list.
    > The generated hardware is only activated on rising edges on the clk
    > signal, so clk shall be the only signal in the sensitivity list.
    >
    > /Peter



    I agree with your opinion and so do most text books I have read. Flips
    flops do not change state on data or enable transitions only. They
    require a clock.

    However it seems the tool designers have a different opinion. All the
    synthesis tools that I have used do not like any signal within a
    process that appears on the right hand side of an assignment statement
    to be left out of the sensitivity list. Otherwise they issue an
    "incomplete sensitivity" list warning.

    The tools seem to know what was intended, so they synthesize the
    design properly anyway, but they also issue the warning. This is fine
    for small designs, but when synthesizing a large design, I do not want
    to wade thru hundreds of these "bogus" warnings when I am only
    interested in "real" warnings or errors that should be corrected.
    Therefore to avoid this I always try to have complete sensitivity
    lists.
    Ralfe Cookson, Jun 4, 2004
    #6
  7. Ralfe Cookson wrote:
    > (Peter Hermansson) wrote in message news:<>...
    >
    >> (Ralfe Cookson) wrote in message news:<>...
    >>
    >>>"MNQ" <> wrote in message news:<c9ne23$qb5$>...
    >>>Note that clock_divide
    >>>should also be in the sensitivity list.
    >>>
    >>> clock_divider : PROCESS (clk, pattern, clock_divide)
    >>> BEGIN
    >>> IF clk='1' AND clk'event THEN
    >>> IF pattern = '1' THEN
    >>> clock_divide <= "00000";
    >>> else
    >>> clock_divide <= clock_divide - 1;
    >>> end if;
    >>> END IF;
    >>> END PROCESS clock_divider;
    >>>

    >>
    >>
    >>I dont agree that pattern and clock_divide shall be in the sensitivity
    >>list.
    >>The generated hardware is only activated on rising edges on the clk
    >>signal, so clk shall be the only signal in the sensitivity list.
    >>
    >>/Peter

    >
    >
    >
    > I agree with your opinion and so do most text books I have read. Flips
    > flops do not change state on data or enable transitions only. They
    > require a clock.
    >
    > However it seems the tool designers have a different opinion. All the
    > synthesis tools that I have used do not like any signal within a
    > process that appears on the right hand side of an assignment statement
    > to be left out of the sensitivity list. Otherwise they issue an
    > "incomplete sensitivity" list warning.
    >
    > The tools seem to know what was intended, so they synthesize the
    > design properly anyway, but they also issue the warning. This is fine
    > for small designs, but when synthesizing a large design, I do not want
    > to wade thru hundreds of these "bogus" warnings when I am only
    > interested in "real" warnings or errors that should be corrected.
    > Therefore to avoid this I always try to have complete sensitivity
    > lists.


    I absolutely disagree with you on this. I have _never_ used a
    _synthesis_ tool that issues a warning in this situation (and I've used
    at least 6 different tools). ModelSim will issue these warnings if you
    turn on "synthesis" checking but this is because this option is, IMO,
    not implemented properly. The ONLY signals that should appear in the
    sensitivity list of a process, that THE SYNTHESIS TOOL RECOGNIZES AS A
    FLIP-FLOP, are asynchronous set/clears and the clock. This is defined in
    the IEEE synthesizable VHDL standard, P1076.6.

    A tool WILL issue warnings if you create a COMBINATIONAL process and
    don't fully specify the sensitivity list.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jun 4, 2004
    #7
  8. MNQ

    JohnP Guest

    Hi Naveen

    What you are doing is not a PLL. But a PLL is the traditional way to sync.
    local and remote clocks. IF you can add an external OpAmp & VCXO to your
    logic device then the VHDL for the Phase Detector is simple.

    Newbie

    "MNQ" <> wrote in message
    news:c9mr9a$5tv$...
    > Hi All
    >
    > I'm trying to write some code to synchronise my local clock with some
    > incoming data. At the moment when the receiver sees a specific bit

    pattern,
    > it makes pattern go to logic 1 for one clock period. This resets my clock
    > and adds a small delay to my 2MHz clock. If I use this method I

    effectively
    > loose a clock cycle which I cannot afford. I want to reset my clock on

    the
    > rising edge of pattern, but when I use the code
    >
    > If pattern='1' and pattern'event then clock_divide<="00010" ;
    >
    > I get a bad synchronous error when I synthesize
    >
    > Am I correct in thinking that this is a digital phase locked loop?
    >
    > Can anyone suggest a way of doing this as I have no idea at the moment and
    > time is slipping by.
    >
    > Thanks for any help
    >
    >
    > clk = 65.536MHz
    > clock_2MHz should be 2.048MHz
    > CPLD is XC2C384
    >
    > clock_divider : PROCESS (clk, pattern)
    > BEGIN
    > IF pattern='1' THEN clock_divide <= "00010";
    > ELSIF clk='1' AND clk'event THEN
    > clock_divide <= clock_divide - 1;
    > END IF;
    > END PROCESS clock_divider;
    >
    > clock_2MHz <= clock_divide(4);
    >
    >
    > --
    > Mr Naveed Qayyum
    >
    > www.mnq.org.uk
    >
    >
    JohnP, Jun 7, 2004
    #8
  9. MNQ

    MNQ Guest

    Hi Newbie
    Do you have any circuits diagrams or some thing that I can use to build a
    VCXO I hav'nt done this in a while?

    thanks

    Naveed
    "JohnP" <> wrote in message
    news:40c4c47a$...
    > Hi Naveen
    >
    > What you are doing is not a PLL. But a PLL is the traditional way to

    sync.
    > local and remote clocks. IF you can add an external OpAmp & VCXO to your
    > logic device then the VHDL for the Phase Detector is simple.
    >
    > Newbie
    >
    > "MNQ" <> wrote in message
    > news:c9mr9a$5tv$...
    > > Hi All
    > >
    > > I'm trying to write some code to synchronise my local clock with some
    > > incoming data. At the moment when the receiver sees a specific bit

    > pattern,
    > > it makes pattern go to logic 1 for one clock period. This resets my

    clock
    > > and adds a small delay to my 2MHz clock. If I use this method I

    > effectively
    > > loose a clock cycle which I cannot afford. I want to reset my clock on

    > the
    > > rising edge of pattern, but when I use the code
    > >
    > > If pattern='1' and pattern'event then clock_divide<="00010" ;
    > >
    > > I get a bad synchronous error when I synthesize
    > >
    > > Am I correct in thinking that this is a digital phase locked loop?
    > >
    > > Can anyone suggest a way of doing this as I have no idea at the moment

    and
    > > time is slipping by.
    > >
    > > Thanks for any help
    > >
    > >
    > > clk = 65.536MHz
    > > clock_2MHz should be 2.048MHz
    > > CPLD is XC2C384
    > >
    > > clock_divider : PROCESS (clk, pattern)
    > > BEGIN
    > > IF pattern='1' THEN clock_divide <= "00010";
    > > ELSIF clk='1' AND clk'event THEN
    > > clock_divide <= clock_divide - 1;
    > > END IF;
    > > END PROCESS clock_divider;
    > >
    > > clock_2MHz <= clock_divide(4);
    > >
    > >
    > > --
    > > Mr Naveed Qayyum
    > >
    > > www.mnq.org.uk
    > >
    > >

    >
    >
    MNQ, Jun 8, 2004
    #9
  10. MNQ

    mike_usa Guest

    Naveed,

    Do you think you can afford width of pattern=1 equal half clock cycle? Or
    even 1/4 (1/8) of clock cycle if you have 4Mhz (8Mhz) clock in your
    circuit? When the width of the patten=1 smaller enough, your
    re-synchronized output clock will look much better. Hopefully it helps.
    process(patter_half, clk)
    begin
    if patter_half = '1' then
    syn_out_clk <= '0';
    else
    syn_out_clk <= clk;
    end if;
    mike_usa, Jun 8, 2004
    #10
  11. MNQ

    JohnP Guest

    The VCXO is a voltage controlled Xtal - many people supply 'em including CTS
    Reeves,
    CMAC, Frequency Controls, Ecmelectronics etc

    Note that VCXOs come in 2 type, fast make and regular. You want fast make
    for prototyping (as you are in a hurry) and regular for manufacture. If your
    PCB
    is crowded choose both types with the same footprint so you can swop out the
    fast make for the regular without having to mount both devices.

    The phase detector VDHL (to get back OT ) is

    entity PLL_Mixer is
    port (
    output: buffer STD_LOGIC;
    clk_in_1: in STD_LOGIC;
    clk_in_2: in STD_LOGIC;
    reset: in STD_LOGIC
    );
    end PLL_Mixer;

    architecture PLL_Mixer_arch of PLL_Mixer is
    signal clear: std_logic;
    signal Q2: std_logic;
    begin

    D_Type1: process (reset, clk_in_1, clear)
    begin
    if reset ='0' then
    output <= '0';
    elsif clear ='1' then output <= '0';
    elsif (clk_in_1 'event and clk_in_1 ='1' ) then
    output <= '1';
    end if;
    end process pll_mixer1;

    D_Type2: process (reset, clk_in_2, clear, output)
    begin
    if reset ='0' then
    Q2 <= '0';
    elsif clear ='1' then
    Q2 <= '0';
    elsif (clk_in_2 'event and clk_in_2 ='1' ) then
    Q2 <= output;
    end if;
    end process pll_mixer2;
    clear <= output AND Q2;
    end pll_mixer_arch;

    The frequency of "output" should be a few kilohertz so you likely will
    have to divide down inputs clk_in_1 and clk_in_2, depending on what these
    are. "output" goes to the OpAmp LP filter which drives the VCXO - Voila !

    Mail me if you want a circuit diag.

    Newbie


    "MNQ" <> wrote in message
    news:ca3mbk$gg5$...
    > Hi Newbie
    > Do you have any circuits diagrams or some thing that I can use to build a
    > VCXO I hav'nt done this in a while?
    >
    > thanks
    >
    > Naveed
    > "JohnP" <> wrote in message
    > news:40c4c47a$...
    > > Hi Naveen
    > >
    > > What you are doing is not a PLL. But a PLL is the traditional way to

    > sync.
    > > local and remote clocks. IF you can add an external OpAmp & VCXO to

    your
    > > logic device then the VHDL for the Phase Detector is simple.
    > >
    > > Newbie
    > >
    > > "MNQ" <> wrote in message
    > > news:c9mr9a$5tv$...
    > > > Hi All
    > > >
    > > > I'm trying to write some code to synchronise my local clock with some
    > > > incoming data. At the moment when the receiver sees a specific bit

    > > pattern,
    > > > it makes pattern go to logic 1 for one clock period. This resets my

    > clock
    > > > and adds a small delay to my 2MHz clock. If I use this method I

    > > effectively
    > > > loose a clock cycle which I cannot afford. I want to reset my clock

    on
    > > the
    > > > rising edge of pattern, but when I use the code
    > > >
    > > > If pattern='1' and pattern'event then clock_divide<="00010" ;
    > > >
    > > > I get a bad synchronous error when I synthesize
    > > >
    > > > Am I correct in thinking that this is a digital phase locked loop?
    > > >
    > > > Can anyone suggest a way of doing this as I have no idea at the moment

    > and
    > > > time is slipping by.
    > > >
    > > > Thanks for any help
    > > >
    > > >
    > > > clk = 65.536MHz
    > > > clock_2MHz should be 2.048MHz
    > > > CPLD is XC2C384
    > > >
    > > > clock_divider : PROCESS (clk, pattern)
    > > > BEGIN
    > > > IF pattern='1' THEN clock_divide <= "00010";
    > > > ELSIF clk='1' AND clk'event THEN
    > > > clock_divide <= clock_divide - 1;
    > > > END IF;
    > > > END PROCESS clock_divider;
    > > >
    > > > clock_2MHz <= clock_divide(4);
    > > >
    > > >
    > > > --
    > > > Mr Naveed Qayyum
    > > >
    > > > www.mnq.org.uk
    > > >
    > > >

    > >
    > >

    >
    >
    JohnP, Jun 9, 2004
    #11
  12. MNQ

    johnp Guest

    And THIS is my corect mail addy - - - sorry for that.
    "JohnP" <> wrote in message news:40c6b9e4
    johnp, Jun 9, 2004
    #12
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Srinivas Kanakapally [MSFT]

    RE: Vs.net Server Explorer Diagram Problems

    Srinivas Kanakapally [MSFT], Jul 8, 2003, in forum: ASP .Net
    Replies:
    0
    Views:
    2,937
    Srinivas Kanakapally [MSFT]
    Jul 8, 2003
  2. BestNews
    Replies:
    0
    Views:
    3,149
    BestNews
    Aug 20, 2003
  3. Susan Baker
    Replies:
    2
    Views:
    800
    kelvSYC
    Jun 26, 2005
  4. Shelly

    Problems, problems for newbie

    Shelly, Sep 2, 2007, in forum: ASP .Net
    Replies:
    1
    Views:
    2,166
    Shelly
    Sep 3, 2007
  5. Sak Na rede
    Replies:
    0
    Views:
    402
    Sak Na rede
    Jan 30, 2009
Loading...

Share This Page