Problems with using to_stdlogicvector()

[SR]

Hi,

On trying to compile the following program, I keep getting errors where
I am using to_stdlogicvector(). I am using bit_vectors since I plan to
write a test bench that reads and writes to a file.

Thanks and I appreciate the consideration.

Mani


library IEEE;
use IEEE.std_logic_1164.all;

entity counter is
port (
reset,ck: in bit;
din : in bit_vector(7 downto 0);
count : out bit_vector(7 downto 0));
end entity counter;

architecture behavioral of counter is
signal cnt: bit_vector(7 downto 0);
begin

counter : process(ck,reset,din) is
variable temp: std_logic_vector(7 downto 0);
variable clk: std_logic;
begin
clk:= to_stdlogicvector(ck);

if reset = '1' then
cnt <= "00000000";
elsif (rising_edge(clk)) then
if cnt = "11111111" then
cnt <= "00000000";
else
temp :=to_stdlogicvector(cnt);
temp := temp+1;
cnt <= to_bitvector(temp);
end if;

end if;
count<= cnt;
end process counter;


end architecture behavioral;

 

[Peter Hermansson]

Hi,

On trying to compile the following program, I keep getting errors where
I am using to_stdlogicvector(). I am using bit_vectors since I plan to
write a test bench that reads and writes to a file.

Thanks and I appreciate the consideration.

Mani


library IEEE;
use IEEE.std_logic_1164.all;

entity counter is
port (
reset,ck: in bit;
din : in bit_vector(7 downto 0);
count : out bit_vector(7 downto 0));
end entity counter;

architecture behavioral of counter is
signal cnt: bit_vector(7 downto 0);
begin

counter : process(ck,reset,din) is
variable temp: std_logic_vector(7 downto 0);
variable clk: std_logic;
begin
clk:= to_stdlogicvector(ck);

if reset = '1' then
cnt <= "00000000";
elsif (rising_edge(clk)) then
if cnt = "11111111" then
cnt <= "00000000";
else
temp :=to_stdlogicvector(cnt);
temp := temp+1;
cnt <= to_bitvector(temp);
end if;

end if;
count<= cnt;
end process counter;


end architecture behavioral;

Hi,

I dont think "to_stdlogicvector" works for bit (ck is a bit and not a
bit-vector) but I also noticed that you use the "+"-operator which is
not defined in std_logic_1164, which is the only library you include.

/Peter

 

[Just an Illusion]

Hi SR,

It seems you have many differents issues ;-)

...
variable clk: std_logic;
begin
clk:= to_stdlogicvector(ck);

Is it not ?
clk := to_stdlogic(ck);

...
temp :=to_stdlogicvector(cnt);

Here it missing logic vector sizes

temp (7 downto 0) := to_stdlogicvector(cnt (7 downto 0));

...
cnt <= to_bitvector(temp);

Same remark
cnt (7 downto 0) := to_bitvector (temp (7 downto 0) );


But why continue to use bit, if you use std_logic locally ?
If you change your bit and bit_vector to std_logic and std_logic_vector,
you have no more problems ;-)

Rgrds,
JaI

 

[Charles M. Elias]

Hi,

On trying to compile the following program, I keep getting errors where
I am using to_stdlogicvector(). I am using bit_vectors since I plan to
write a test bench that reads and writes to a file.

Thanks and I appreciate the consideration.

Mani


library IEEE;
use IEEE.std_logic_1164.all;

entity counter is
port (
reset,ck: in bit;
din : in bit_vector(7 downto 0);
count : out bit_vector(7 downto 0));
end entity counter;

architecture behavioral of counter is
signal cnt: bit_vector(7 downto 0);
begin

counter : process(ck,reset,din) is
variable temp: std_logic_vector(7 downto 0);
variable clk: std_logic;
begin
clk:= to_stdlogicvector(ck);

if reset = '1' then
cnt <= "00000000";
elsif (rising_edge(clk)) then
if cnt = "11111111" then
cnt <= "00000000";
else
temp :=to_stdlogicvector(cnt);
temp := temp+1;
cnt <= to_bitvector(temp);
end if;

end if;
count<= cnt;
end process counter;


end architecture behavioral;

cnt + 1 is not a legal operation for bit_vector or std_logic_vector;
it is for unsigned.

I have redone your logic as shown below. Unless you have a compelling
reason for using bit vectors in your I/O, the design is made easier in
this case by using std_logic_vector. By the way din is unused. If
you use it to load the counter you can do this as part of the logic:

if load = '1' then --load is a new signal input
cnt <= unsigned( din );

Charles

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
port (
reset, ck : in std_logic_vector;
din : in std_logic_vector(7 downto 0);
count : out std_logic_vector(7 downto 0)
);
end entity counter;

architecture behavioral of counter is

signal cnt: unsigned(7 downto 0);

begin

counter : process(ck,reset,din) is

begin

if reset = '1' then
cnt <= "00000000";
elsif (rising_edge(clk)) then
if cnt = "11111111" then
cnt <= "00000000";
else
cnt <= cnt + 1;
end if;

end if;
count <= std_logic_vector( cnt );
end process counter;