procedure as argument in procedure

A

AlexWare

Hello everybody,

in a behavioral model I would like to pass a procedure as argument in
a procedure call.
I read that formal parameters in a subprogram can be only constants,
variables or signals; is there any, usual or recommended way to do
what I need?

Thanks.


Alex
 
K

Kenn Heinrich

AlexWare said:
Hello everybody,

in a behavioral model I would like to pass a procedure as argument in
a procedure call.
I read that formal parameters in a subprogram can be only constants,
variables or signals; is there any, usual or recommended way to do
what I need?

No. You're stuck, as far as I can tell. If you have a very small
universe of procedures you might want to call, you can pass a token
(e.g. a number) to say which function you meant to call, then manually
dispatch inside the procedure by switching on the token.

Otherwise, you can create your design using another language (LISP,
Haskell, etc) that can do these sorts of things and then translate,
but that could easily turn into a thesis project!

- Kenn
 
P

Paul Uiterlinden

AlexWare said:
Hello everybody,

in a behavioral model I would like to pass a procedure as argument in
a procedure call.
I read that formal parameters in a subprogram can be only constants,
variables or signals; is there any, usual or recommended way to do
what I need?

The closest thing that comes to mind is VHDL-2008. Note however that as far
as I know the features needed here have not yet been implemented in any
simulator.

What you could use is a procedure with a generic. That generic then would
not be a generic constant as we know it today, but a generic subprogram
instead.

VHDL-2008 has expanded the capabilities of "generics" in two ways.

Firstly, the things that we usually call a generic is actually a generic
constant. That has changed in VHDL-2008: besides generic constants you can
now have generic types and generic subprograms as well. That means that you
can pass a type, procedure or function through a generic map.

Secondly, generics can be applied on subprograms (and packages) in
VHDL-2008. But to use such a subprogram, it must first be instantiated one
or multiple times, with a generic map, resulting in different versions of
the original subprogram.

The book VHDL-2008 by Ashenden/Lewis has lots of more details.

But as said above, it is not usable at the moment by the lack of support of
simulators. And I don't know if the solution is applicable to your problem.
 

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