procedure and actual parameters

[Al]

Hi everyone, I have this simple procedure which will call two times
another procedure, in which I give actual parameters to assign values.
These actuals are declared in a package so that they can be visible to
all the procedures in any part of the hierarchy.

procedure WRITEop (
ctrl : in string;
data : in string) is
begin

send_data (strobe, write, select, data, io);
send_data (strobe, write, select, ctrl, io);

end procedure;

unfortunately this doesn't compile with Modelsim and the error message
is the following:

# ** Error: ../SlowControl_st.vhd(197): Cannot drive signal 'sc_write' from this subprogram.
# ** Error: ../SlowControl_st.vhd(197): Cannot drive signal 'sc_select' from this subprogram.
# ** Error: ../SlowControl_st.vhd(197): Cannot drive signal 'sc_io' from this subprogram.
# ** Error: ../SlowControl_st.vhd(239): No feasible entries for subprogram "send_data".
# ** Error: ../SlowControl_st.vhd(280): No feasible entries for subprogram "send_data".
# ** Error: ../SlowControl_st.vhd(325): No feasible entries for subprogram "send_data".
# ** Error: ../SlowControl_st.vhd(341): No feasible entries for subprogram "send_data".

The "send_data" procedure is the following:

procedure send_data(
signal strb : out std_logic;
signal wr : out std_logic;
signal sel : out std_logic;
data : in string;
signal IO_reg : out std_logic_vector (15 downto 0)
) is

variable data_send : std_logic_vector (15 downto 0);
variable data_line : line;

begin

sel <= '1';
write(data_line, data);
hread(data_line, data_send);
wr <= '0';
strb <= '0';
IO_reg <= (others => 'Z');
wait until rising_edge (clk);
wr <= '1';
wait for 7 ns;
IO_reg <= data_send;
wait until rising_edge (clk);
strb <= '1';
wait until rising_edge (clk);
strb <= '0';
wr <= '0';
wait for 4 ns;
IO_reg <= (others => 'Z');
end procedure;

I wanted to make a procedure which can make different operations calling
other procedures, without the need to pass these actual parameters all
the time.
Have I been clear? (sorry but i don't think is a matter of language,
just a matter of my mind!)
Do you have any suggestions?

Al

 

[Andy]

A procedure not declared in a process cannot drive signals not passed
explicitly to it. This has to do with locally statically being able to
determine the signals that a process (implied or explicit) drives.
This has been covered in recent threads here.

To simplify the parameter passing, you can create one or more records
for the ports. The only problem is that VHDL currently only allows a
single mode for the entire record, and all of its elements. Supposedly
they're working on that... For now, you can use inout, but that means
that all of the elements have to be resolved types, and you must
remember to drive "inputs" with 'Z's from within the procedures, so
that the default driver value ('U') does not conflict with whoever is
trying to drive it with a real value. The necessity of resolving all
those signals also eats simulation performance.

Andy

 

[Mike Treseler]

I wanted to make a procedure which can make different operations calling
other procedures, without the need to pass these actual parameters all
the time.

Either declare or overload the
procedure in the calling process.
Read today's posing in the thread
"Re: RFC on VHDL LRM 93[8.4.1]"

-- Mike Treseler

 

[Al]

Either declare or overload the
procedure in the calling process.
Read today's posing in the thread
"Re: RFC on VHDL LRM 93[8.4.1]"

-- Mike Treseler

I got the point, I should have read that thread before posting mine!
Thanks

Al