Process...

[VHDL User]

Hi All,
I have a very basic doubt,which may probably have been answered before,
but nevertheless, here it is:
Is a process with NO wait and NO sensitivity list executed only once
(at the start of the simulation) or forever ? As in,
process ()
begin
A<=B and C;
end process

Suppose B and C are changed in some other part of the code.Then,will A
change at all ? that is,will the process keep executing ?
Also,if I synthesise this process, will there be anything generated at
all,since there is no sensitivity list?
Thanks a lot,
Bye

 

[Jim Lewis]

Actually quite the opposite. If you write your process
without a sensitivity list, it runs until it hits a wait
statement. If there is no wait statement, it loops
continuously. This is bad as it loops without any
time passing (including delta cycles) and if the simulator
does not detect it, then the simulation hangs.

The behavior of what your proposed circuit does is
consistent with the following. The following creates
a clock waveform with a period of 20 ns that runs forever.


ClkProc : process
begin
Clk <= '0' ;
wait for 10 ns ;
Clk <= '1' ;
wait for 10 ns ;
end process ;

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
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1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[VHDL User]

Actually quite the opposite. If you write your process
without a sensitivity list, it runs until it hits a wait
statement. If there is no wait statement, it loops continuously.

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Is this a simulator dependent phenomenon or is it specified in the VHDL
language reference ?? While what you say is consistent with Verilog always
construct, it doesnt somehow fit in with the functioning of wait
statement.
When in the execution of a process, simulator encounters a wait, it
waits until the wait condition is satisfied. The release from wait
generates a event causing scheduling of the process to be executed at the
next free delta cycle.So,after completing the process, the scheduled event
is executed,i.e, the process is executed again. This is what happens in
your example of Clock generation.
However,if there is no wait statement, then WHY should there be a
process (re)execution event scheduled for the future ?
Thanks a lot for your reply.
Bye.

 

[Alan Fitch]

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Is this a simulator dependent phenomenon or is it specified in the VHDL
language reference ?? While what you say is consistent with Verilog always
construct, it doesnt somehow fit in with the functioning of wait
statement.
When in the execution of a process, simulator encounters a wait, it
waits until the wait condition is satisfied. The release from wait
generates a event causing scheduling of the process to be executed at the
next free delta cycle.So,after completing the process, the scheduled event
is executed,i.e, the process is executed again. This is what happens in
your example of Clock generation.
However,if there is no wait statement, then WHY should there be a
process (re)execution event scheduled for the future ?
Thanks a lot for your reply.
Bye.

<snip>

In VHDL processes always execute in a loop continuously, unless there
is a means of suspending them. Your idea that the resumption of the
process after a wait generates an event is not correct. All processes
"want" to execute all the time unless they are suspended.

Your statement "at the next free delta cycle" is also not quite right.
The basic operation of the scheduler is

1. processes run until they suspend (the evaluate phase)
During evaluation, assignments to signals are made.

2. when *all* processes have suspended in the design, the
simulator updates any signals that may have been assigned
(the update phase)

3. Updating the signals may cause events that trigger processes
to run again without time advancing - if so go back to step 1

4. advance time

5. advancing time may result in timeouts occuring (e.g. wait for 10
ns
resumes)
or signals changing value (e.g. s <= '0', '1' after 10 ns If so
mark those processes as "need to run" and go back to step 1

6. if no events are scheduled and no timeouts are pending,
simulation ends


The loop from 1 to 3 is the delta cycle.

This a simplified description of the scheduler - see the LRM for the
full
details.


The basic point (compared to your original post) is that all processes
must
suspend before time can advance (either "real" time or a delta cycle
step).

So if a process has no wait statements and no sensitivity list, the
simulator
cannot advance and will get stuck in a loop.

This behaviour is described in the LRM.

regards

Alan


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[Srinivasan Venkataramanan]

Hi,
In addition to Alan's excellent "quick ref" on VHDL Scheduling, since you
are comparing it against Verilog, here is a simple mapping:

Verilog VHDL
--------------------
always process
initial process with a "wait;" at the end

i.e. there is no direct counter-part to Verilog's initial.

HTH,
Srinivasan
--
Srinivasan Venkataramanan
Corp. Appl. Engineer
Synopsys India Pvt. Ltd.
Bangalore, India
email:synopsys.com@svenkat
I own my words and not my employer, unless specifically mentioned

 

[srikanth.padava]

delta cycle??

That was a good explanation by Alan Fitch. But i still have a basic question regarding the delta cycle. It has really got on to my head now. I hope some one could help me out with this.

As alan described in his post that a
1. delta cycle = evaluation phase+update phase.
2. and i have read that a signal gets updated only after one delta cycle delay.
i.e if a process has a stmt a=1;(im using systemc) and deltacount =0, it should be updated in the next cycle.
3. but from alan, if stmt a=1 gets evaluated in the present deltacycle, and gets updated in the update phase(which is also in the same deltacycle, as it was told that delta cycle = evaluation phase+update phase.)

it would be great if some one explains me where ive got it wrong.

thanx a lot in advance,

srikanth.