F
fskalka
We have some programming files (we have rights to the source, and have
hardcopy of the source in schematics, no softcopy) for some ACTEL
FPGAs (AT1240XL and AT1225XL). We are in the process of creating VHDL
code for these parts so we can make changes and do some integration.
We would like to do some simulation to verify our new code against the
old design before we put our new code in hardware.
Does anybody know of a way to create a black box simulation model
(preferably VHDL) for the FPGAs from the programming file? I realize
that a net list is not usable, but the should be able to extract the
input to output logic and timing based on fuse map information.
hardcopy of the source in schematics, no softcopy) for some ACTEL
FPGAs (AT1240XL and AT1225XL). We are in the process of creating VHDL
code for these parts so we can make changes and do some integration.
We would like to do some simulation to verify our new code against the
old design before we put our new code in hardware.
Does anybody know of a way to create a black box simulation model
(preferably VHDL) for the FPGAs from the programming file? I realize
that a net list is not usable, but the should be able to extract the
input to output logic and timing based on fuse map information.