Quartus v6.0 problem

[Boris Ozegovic]

Hi

Below is the Mealy sequence detector (10100111) code. I downloaded Quartus
6.0 Web edition, and when I run simulation I get this waveform
<http://www.inet.hr/~bozegov/dijagram.jpg>. I did exactly the same
procedure at my college, and everything worked perfecty?! What seems to be
the problem? :-/

entity automat3 is
port ( x, clk : in bit;
z : out bit );
end automat3;

architecture ponasanje of automat3 is
type state is (a, b, c, d, e, f, g, h);
signal currentState : stanje := a;
signal nextState : stanje := a;
signal nextZ : bit;

begin

kombinacijski : process ( x, currentState )
begin
nextZ <= '0';
case currentState is
when a =>
if ( x = '1' ) then
nextState <= b;
else
nextState <= a;
end if;
when b =>
if ( x = '1' ) then
nextState <= b;
else
nextState <= c;
end if;
when c =>
if ( x = '1' ) then
nextState <= d;
else
nextState <= a;
end if;
when d =>
if ( x = '1' ) then
nextState <= b;
else
nextState <= e;
end if;
when e =>
if ( x = '1' ) then
nextState <= d;
else
nextState <= f;
end if;
when f =>
if ( x = '1' ) then
nextState <= g;
else
nextState <= a;
end if;
when g =>
if ( x = '1' ) then
nextState <= h;
else
nextState <= c;
end if;
when h =>
if ( x = '1' ) then
nextState <= a;
nextZ <= '1';
else
nextState <= c;
end if;
end case;
end process kombinacijski;

clock : process ( clk )
begin
if ( clk'event and clk = '1' ) then
currentState <= sljedeceStanje;
z <= nextZ;
end if;
end process clock;

end ponasanje;

 

[Boris Ozegovic]

architecture ponasanje of automat3 is
type state is (a, b, c, d, e, f, g, h);
signal currentState : stanje := a;
signal nextState : stanje := a;
signal nextZ : bit;

Sorry, stanje == state.

clock : process ( clk )
begin
if ( clk'event and clk = '1' ) then
currentState <= sljedeceStanje;
z <= nextZ;

sljedeceStanje == nextState