RAM initialization

Discussion in 'VHDL' started by Mario, May 31, 2004.

  1. Mario

    Mario Guest

    Hello,

    I am new in VHDL and I would like to make a question.

    I saw in a site a RAM code and manipulated it to make a 15 bit address an 8
    bit word RAM (32k)

    Is there a possible way to initialize this RAM using an external file and
    how?How this file should look like?

    Here is the code :

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity RAM_32K is
    port (
    CLK : in std_logic;
    WE : in std_logic; -- write enable
    EN : in std_logic;
    addr : in std_logic_vector(14 downto 0);
    datain : in std_logic_vector(7 downto 0);
    dataout : out std_logic_vector(7 downto 0));
    end RAM_32K;

    architecture RAM32 of RAM_32K is
    type ram_type is array(32767 downto 0) of std_logic_vector(7 downto 0);
    signal ram : ram_type;
    begin
    process(CLK)
    begin
    if (CLK'event and CLK = '1') then
    if (en = '1') then
    if (we = '1') then
    ram(conv_integer(addr)) <= datain;
    dataout <= datain;
    else dataout <= ram(conv_integer(addr));
    end if;
    end if;
    end if;
    end process;
    end;
     
    Mario, May 31, 2004
    #1
    1. Advertising

  2. "Mario" <> wrote in message news:<c9g7pu$7lr$>...

    > Is there a possible way to initialize this RAM using an external file


    This has been covered in comp.arch.fpga:
    http://groups.google.com/groups?q=fpga initialize ram

    I have modified your code (below) as an example of
    how to use the numeric_std library.

    Since you asked the vhdl newsgroup,
    here's my vhdl skewed take on blockram initialization:

    Why might I want to init a blockram during download?
    There are two possible reasons.

    1. I really need a rom, and should consider using a vhdl
    constant array of vectors to infer the ROM from
    block RAM without worrying about vendor specific files.

    2. I have a local or external controller that
    will do read and write cycles to this block ram.
    In this case, consider inferring the RAM from
    a template and init it (if need be) using the controller.

    -- Mike Treseler
    --------------------------------------------------------------
    > Here is the code :


    -- modified to use numeric_std
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity RAM_32K is
    port (
    CLK : in std_logic;
    WE : in std_logic; -- write enable
    EN : in std_logic;
    addr : in std_logic_vector(14 downto 0);
    datain : in std_logic_vector(7 downto 0);
    dataout : out std_logic_vector(7 downto 0));
    end RAM_32K;

    architecture RAM32 of RAM_32K is
    type ram_type is array(32767 downto 0)
    of std_logic_vector(7 downto 0);
    signal ram : ram_type;
    begin
    process(CLK)
    begin
    if (CLK'event and CLK = '1') then
    if (en = '1') then
    if (we = '1') then
    ram(to_integer(unsigned(addr))) <= datain;
    dataout <= datain;
    else
    dataout <= ram(to_integer(unsigned(addr)));
    end if;
    end if;
    end if;
    end process;
    end;
     
    Mike Treseler, Jun 1, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Robert Posey
    Replies:
    0
    Views:
    678
    Robert Posey
    Nov 26, 2003
  2. JKop
    Replies:
    10
    Views:
    948
  3. ashu
    Replies:
    1
    Views:
    462
  4. ashu
    Replies:
    2
    Views:
    616
    mysticlol
    Nov 6, 2006
  5. Xin Xiao

    Block RAM Distributed RAM

    Xin Xiao, Jan 7, 2008, in forum: VHDL
    Replies:
    8
    Views:
    1,476
    Duane Clark
    Jan 7, 2008
Loading...

Share This Page