ram not infering as block ram

Discussion in 'VHDL' started by ashu, Nov 3, 2006.

  1. ashu

    ashu Guest

    hi
    i had written a code for ram but synthesis tool (SYNPLIFY PRO) is not
    infering it as block ram in fact it is
    using luts which is consuming lot of chip area.... i m using ALTERA
    CYCLONE attribute syn_ramstyle is working well for xilinx device but
    not for altera .....could somebody suggest any remedy....code is given
    below

    thanks
    ashwani anand
    ---------------- --------------- --------------

    library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.std_logic_unsigned.all ;
    use ieee.std_logic_arith.all ;

    entity ram is

    port (
    pclk,sclk,r,w : in std_logic ;
    read_a , write_a : in std_logic_vector(11 downto 0 );
    data_in : in std_logic_vector(25 downto 0 ) ;
    data_out : out std_logic_vector(25 downto 0 )

    ) ;

    end ram ;

    architecture a of ram is

    type temp is array ( 4095 downto 0 ) of std_logic_vector(25 downto 0) ;

    signal t_ram : temp ;

    begin


    process ( pclk,w ) --------- writing in ram

    begin

    if ( pclk'event and pclk = '1' ) then

    if (w = '1') then

    t_ram( conv_integer ( unsigned(write_a ))) <= data_in ;

    else


    end if ;

    end if ;

    end process ;


    process ( sclk,r ) -----------reading from ram

    begin

    if ( sclk'event and sclk = '1' ) then

    if (r = '1') then

    data_out <= t_ram( conv_integer ( unsigned(read_a ))) ;

    else

    data_out <= (others => '0' ) ;

    end if ;

    end if ;

    end process ;
    end a ;
    ashu, Nov 3, 2006
    #1
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  2. ashu

    radarman Guest

    ashu wrote:
    > hi
    > i had written a code for ram but synthesis tool (SYNPLIFY PRO) is not
    > infering it as block ram in fact it is
    > using luts which is consuming lot of chip area.... i m using ALTERA
    > CYCLONE attribute syn_ramstyle is working well for xilinx device but
    > not for altera .....could somebody suggest any remedy....code is given
    > below
    >
    > thanks
    > ashwani anand
    > ---------------- --------------- --------------
    >
    > library ieee ;
    > use ieee.std_logic_1164.all ;
    > use ieee.std_logic_unsigned.all ;
    > use ieee.std_logic_arith.all ;
    >
    > entity ram is
    >
    > port (
    > pclk,sclk,r,w : in std_logic ;
    > read_a , write_a : in std_logic_vector(11 downto 0 );
    > data_in : in std_logic_vector(25 downto 0 ) ;
    > data_out : out std_logic_vector(25 downto 0 )
    >
    > ) ;
    >
    > end ram ;
    >
    > architecture a of ram is
    >
    > type temp is array ( 4095 downto 0 ) of std_logic_vector(25 downto 0) ;
    >
    > signal t_ram : temp ;
    >
    > begin
    >
    >
    > process ( pclk,w ) --------- writing in ram
    >
    > begin
    >
    > if ( pclk'event and pclk = '1' ) then
    >
    > if (w = '1') then
    >
    > t_ram( conv_integer ( unsigned(write_a ))) <= data_in ;
    >
    > else
    >
    >
    > end if ;
    >
    > end if ;
    >
    > end process ;
    >
    >
    > process ( sclk,r ) -----------reading from ram
    >
    > begin
    >
    > if ( sclk'event and sclk = '1' ) then
    >
    > if (r = '1') then
    >
    > data_out <= t_ram( conv_integer ( unsigned(read_a ))) ;
    >
    > else
    >
    > data_out <= (others => '0' ) ;
    >
    > end if ;
    >
    > end if ;
    >
    > end process ;
    > end a ;


    One post will do better than two.

    You are probably attempting to synthesize a RAM that the tools either
    don't recognize, or that the chip doesn't support.

    For example, Altera BRAM's require a registered address and
    wr_en/rd_en. If you don't infer the flops in your HDL, you end up with
    LUTs instead. Check the datasheet of your target device, and find out
    what modes the block RAM's support, then write HDL that infers the
    desired, and supported, behavior.
    radarman, Nov 3, 2006
    #2
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  3. ashu

    mysticlol Guest

    You are trying to infer Dual Port RAM and your code is correct for
    that.
    This seems to be ALTERA FPGA related issue.

    I was going through Synplify User Guide and I found that
    "......
    2. To use the dedicated memory resources on the FPGA (Altera
    technologies), do the following:

    - Set syn_ramstyle to block_ram.

    - For Flex10K architectures, register the read address, because the
    technology does not support dual port RAMs.

    -- Include an explicit read address register.
    The address must be registered to implement a synchronous RAM in
    an LPM.
    ....."

    modify the read process..May be something like this.

    signal reg_rd_add : std_logic_vector(11 downto 0);

    process(sclk, r)
    begin
    if rising_edge(sclk) then
    if r='1' then
    reg_rd_add <= read_a;
    end if;
    end if;
    end process;

    data_out <= t_ram( conv_integer ( unsigned(reg_rd_add))) ;

    regards,
    JK


    ashu wrote:
    > hi
    > i had written a code for ram but synthesis tool (SYNPLIFY PRO) is not
    > infering it as block ram in fact it is
    > using luts which is consuming lot of chip area.... i m using ALTERA
    > CYCLONE attribute syn_ramstyle is working well for xilinx device but
    > not for altera .....could somebody suggest any remedy....code is given
    > below
    >
    > thanks
    > ashwani anand
    > ---------------- --------------- --------------
    >
    > library ieee ;
    > use ieee.std_logic_1164.all ;
    > use ieee.std_logic_unsigned.all ;
    > use ieee.std_logic_arith.all ;
    >
    > entity ram is
    >
    > port (
    > pclk,sclk,r,w : in std_logic ;
    > read_a , write_a : in std_logic_vector(11 downto 0 );
    > data_in : in std_logic_vector(25 downto 0 ) ;
    > data_out : out std_logic_vector(25 downto 0 )
    >
    > ) ;
    >
    > end ram ;
    >
    > architecture a of ram is
    >
    > type temp is array ( 4095 downto 0 ) of std_logic_vector(25 downto 0) ;
    >
    > signal t_ram : temp ;
    >
    > begin
    >
    >
    > process ( pclk,w ) --------- writing in ram
    >
    > begin
    >
    > if ( pclk'event and pclk = '1' ) then
    >
    > if (w = '1') then
    >
    > t_ram( conv_integer ( unsigned(write_a ))) <= data_in ;
    >
    > else
    >
    >
    > end if ;
    >
    > end if ;
    >
    > end process ;
    >
    >
    > process ( sclk,r ) -----------reading from ram
    >
    > begin
    >
    > if ( sclk'event and sclk = '1' ) then
    >
    > if (r = '1') then
    >
    > data_out <= t_ram( conv_integer ( unsigned(read_a ))) ;
    >
    > else
    >
    > data_out <= (others => '0' ) ;
    >
    > end if ;
    >
    > end if ;
    >
    > end process ;
    > end a ;
    mysticlol, Nov 6, 2006
    #3
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