record of a record to std_logic_vector

Discussion in 'VHDL' started by THurkmans, Aug 26, 2009.

  1. THurkmans

    THurkmans Guest

    Hello,

    I've made a design in which I have a few blocks which I want to
    synthesize. My simulation is working, and now I'm trying to do a post-
    synthesis simulation per block by replacing each block with its
    synthesized version.

    What I didn't expect from my synthesis tool was that it would mess up
    my entities in which I use records. I have created a small records to
    pass my memories to my block:

    type ram_image_type is record
    enable : std_logic;
    write_enable : std_logic;
    address : std_logic_vector(17 downto 0);
    inoutput : std_logic_vector(7 downto 0);
    end record;

    type memories_inout_type is record
    image0 : ram_image_type;
    image1 : ram_image_type;
    image2 : ram_image_type;
    end record;

    I've found posts which create to_vec and from_vec, and align the
    vectors such that they can be used in one std_logic_vector, but those
    only assume one record. How can I create a to_std_logic_vector for the
    memories_inout_type record?
    THurkmans, Aug 26, 2009
    #1
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  2. THurkmans

    Andy Guest

    On Aug 26, 4:19 am, THurkmans <> wrote:
    > Hello,
    >
    > I've made a design in which I have a few blocks which I want to
    > synthesize. My simulation is working, and now I'm trying to do a post-
    > synthesis simulation per block by replacing each block with its
    > synthesized version.
    >
    > What I didn't expect from my synthesis tool was that it would mess up
    > my entities in which I use records. I have created a small records to
    > pass my memories to my block:
    >
    > type ram_image_type is record
    >         enable : std_logic;
    >         write_enable : std_logic;
    >         address : std_logic_vector(17 downto 0);
    >         inoutput : std_logic_vector(7 downto 0);
    > end record;
    >
    > type memories_inout_type is record
    >         image0 : ram_image_type;
    >         image1 : ram_image_type;
    >         image2 : ram_image_type;
    > end record;
    >
    > I've found posts which create to_vec and from_vec, and align the
    > vectors such that they can be used in one std_logic_vector, but those
    > only assume one record. How can I create a to_std_logic_vector for the
    > memories_inout_type record?


    Maybe create a function which calls the little "record_to_slv"
    function for each sub-record, concatenating the results?

    BTW, anytime you have a record which contains three (or 'N') identical
    items, it should probably be an array, not a record. Arrays allow you
    to index the elements using loops, variables/signals, etc.

    Andy
    Andy, Aug 26, 2009
    #2
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  3. THurkmans

    KJ Guest

    On Aug 26, 5:19 am, THurkmans <> wrote:

    >
    > I've found posts which create to_vec and from_vec, and align the
    > vectors such that they can be used in one std_logic_vector, but those
    > only assume one record. How can I create a to_std_logic_vector for the
    > memories_inout_type record?


    By first creating to_vec and from_vec functions that work with
    'ram_image_type'. Then the to_vec and from_vec for
    'memories_inout_type' would call the to_vec and from_vec for each of
    the elements of the record. One possible way is...

    function to_vec(R: memories_inout_type) is
    begin
    return(to_vec(R.image0) & to_vec(R.image1) & to_vec(R.image2));
    end function to_vec;

    To do the 'from_vec' function you'd have to know the size of the
    vector that is returned from the 'from_vec' function that works with
    'ram_image_type' so that you can strip out the appropriate set of bits
    so that you can then call from_vec with it.

    Kevin Jennings
    KJ, Aug 26, 2009
    #3
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