In detail, 0.8 ns is the time that you dispose from the falling edge of
"clock" to the ADSP stable signal, mesured BOTH at the input of the
cypress device.
If "clock" is delivered by your VHDL device, it is relatively easy to
assure that all propagation times may be close together between clock and
and other lines.
But if clock is issued by another device and only used by both you VHDL
device and the Cypress one, you have to look very close to all that.
I think 0.8 ns is very short time. I synthesised my component:
Source: S_THIS_9 (FF)
Destination: P_O_DQ<10> (PAD)
Source Clock: P_I_CLK falling
Data Path: S_THIS_9 to P_O_DQ<10>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 34 0.307 1.360 S_THIS_9 (S_THIS_9)
LUT2:I1->O 1 0.195 0.534 _n0003<1>1
(Mtridata_P_O_DQ<1>)
OBUFT:I->O 3.957 P_O_DQ_1_OBUFT (P_O_DQ<1>)
----------------------------------------
Total 6.353ns (4.459ns logic, 1.894ns route)
(70.2% logic, 29.8% route)
and that is report:
Why are there 4 clocks?
If 6 ns is necessary, i would have to use about 100 MHz clock...
I do not know if i can use clocks slower than written in pdf..
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <use_sram>.
Related source file is "C:/Xilinx/nanowo/sram.vhdl".
WARNING:Xst:647 - Input <P_I_RW> is never used.
WARNING:Xst:647 - Input <P_I_Ready> is never used.
WARNING:Xst:736 - Found 11-bit latch for signal <Mtridata_P_O_Data> created
at line 131.
WARNING:Xst:736 - Found 11-bit latch for signal <Mtridata_P_O_DQ> created at
line 132.
Using one-hot encoding for signal <S_THIS>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <S_THIS> of Case statement line
70 was re-encoded using one-hot encoding. The case statement will be
optimized (default statement optimization), but this optimization may lead
to design initialization problems. To ensure the design works safely, you
can:
- add an 'INIT' attribute on signal <S_THIS> (optimization is then done
without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a
safe (but less efficient) optimization
Found 4x2-bit ROM for signal <$n0009>.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_P_O_Data> created at
line 131.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data
and gate enable inputs of this latch share common terms. This situation will
potentially lead to setup/hold violations and, as a result, to simulation
problems. This situation may come from an incomplete case statement (all
selector values are not covered). You should carefuly review if it was in
your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_P_O_DQ> created at
line 132.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data
and gate enable inputs of this latch share common terms. This situation will
potentially lead to setup/hold violations and, as a result, to simulation
problems. This situation may come from an incomplete case statement (all
selector values are not covered). You should carefuly review if it was in
your intentions to describe such a latch.
WARNING:Xst:737 - Found 10-bit latch for signal <S_NEXT>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data
and gate enable inputs of this latch share common terms. This situation will
potentially lead to setup/hold violations and, as a result, to simulation
problems. This situation may come from an incomplete case statement (all
selector values are not covered). You should carefuly review if it was in
your intentions to describe such a latch.
Found 11-bit tristate buffer for signal <P_O_DQ>.
Found 11-bit tristate buffer for signal <P_O_Data>.
Found 10-bit register for signal <S_THIS>.
Summary:
inferred 1 ROM(s).
inferred 22 Tristate(s).
Unit <use_sram> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 1
4x2-bit ROM : 1
# Registers : 1
10-bit register : 1
# Latches : 5
1-bit latch : 2
10-bit latch : 1
11-bit latch : 2
# Tristates : 2
11-bit tristate buffer : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# ROMs : 1
4x2-bit ROM : 1
# Registers : 10
Flip-Flops : 10
# Latches : 5
1-bit latch : 2
10-bit latch : 1
11-bit latch : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch S_NEXT_0 hinder the
constant cleaning in the block use_sram.
You should achieve better results by setting this init to 0.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_10> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_9> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_8> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_7> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_6> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_5> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_4> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_3> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_2> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_1> is equivalent to a wire in
block <use_sram>.
WARNING:Xst:1294 - Latch <Mtridata_P_O_DQ_0> is equivalent to a wire in
block <use_sram>.
Loading device for application Rf_Device from file '4vlx15.nph' in
environment C:\Xilinx.
Optimizing unit <use_sram> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block use_sram, actual ratio is
0.
FlipFlop S_THIS_2 has been replicated 5 time(s) to handle iob=true
attribute.
Latch Mtrien_P_O_Data has been replicated 10 time(s) to handle iob=true
attribute.
Latch Mtrien_P_O_DQ has been replicated 10 time(s) to handle iob=true
attribute.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : use_sram.ngr
Top Level Output File Name : use_sram
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 100
Cell Usage :
# BELS : 35
# GND : 1
# LUT2 : 15
# LUT3 : 19
# FlipFlops/Latches : 58
# FDC_1 : 14
# FDP_1 : 1
# LD : 33
# LD_1 : 10
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 97
# IBUF : 42
# OBUF : 33
# OBUFT : 22
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 4vlx15sf363-10
Number of Slices: 34 out of 6144 0%
Number of Slice Flip Flops: 20 out of 12288 0%
Number of 4 input LUTs: 34 out of 12288 0%
Number of bonded IOBs: 98 out of 240 40%
IOB Flip Flops: 38
Number of GCLKs: 1 out of 32 3%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
_n0021(_n00211:O) | NONE(*)(Mtrien_P_O_DQ) | 22 |
S_THIS_9 | NONE | 10 |
P_I_CLK | BUFGP | 15 |
S_THIS_4 | NONE | 11 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically
buffered by XST with BUFG/BUFR resources. Please use the buffer_type
constraint in order to insert these buffers to the clock signals to help
prevent skew problems.
Timing Summary:
---------------
Speed Grade: -10
Minimum period: No path found
Minimum input arrival time before clock: 1.890ns
Maximum output required time after clock: 6.353ns
Maximum combinational path delay: 6.415ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'S_THIS_4'
Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset: 1.890ns (Levels of Logic = 1)
Source: P_I_DQ<10> (PAD)
Destination: Mtridata_P_O_Data_10 (LATCH)
Destination Clock: S_THIS_4 falling
Data Path: P_I_DQ<10> to Mtridata_P_O_Data_10
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.965 0.534 P_I_DQ_10_IBUF
(P_I_DQ_10_IBUF)
LD
0.391 Mtridata_P_O_Data_10
----------------------------------------
Total 1.890ns (1.356ns logic, 0.534ns route)
(71.8% logic, 28.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'P_I_CLK'
Total number of paths / destination ports: 64 / 40
-------------------------------------------------------------------------
Offset: 6.353ns (Levels of Logic = 2)
Source: S_THIS_9 (FF)
Destination: P_O_DQ<10> (PAD)
Source Clock: P_I_CLK falling
Data Path: S_THIS_9 to P_O_DQ<10>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 34 0.307 1.360 S_THIS_9 (S_THIS_9)
LUT2:I1->O 1 0.195 0.534 _n0003<1>1
(Mtridata_P_O_DQ<1>)
OBUFT:I->O 3.957 P_O_DQ_1_OBUFT (P_O_DQ<1>)
----------------------------------------
Total 6.353ns (4.459ns logic, 1.894ns route)
(70.2% logic, 29.8% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'S_THIS_4'
Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset: 4.964ns (Levels of Logic = 1)
Source: Mtridata_P_O_Data_10 (LATCH)
Destination: P_O_Data<10> (PAD)
Source Clock: S_THIS_4 falling
Data Path: Mtridata_P_O_Data_10 to P_O_Data<10>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.473 0.534 Mtridata_P_O_Data_10
(Mtridata_P_O_Data_10)
OBUFT:I->O 3.957 P_O_Data_10_OBUFT
(P_O_Data<10>)
----------------------------------------
Total 4.964ns (4.430ns logic, 0.534ns route)
(89.2% logic, 10.8% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0021'
Total number of paths / destination ports: 22 / 22
-------------------------------------------------------------------------
Offset: 4.964ns (Levels of Logic = 1)
Source: Mtrien_P_O_Data_1 (LATCH)
Destination: P_O_Data<10> (PAD)
Source Clock: _n0021 falling
Data Path: Mtrien_P_O_Data_1 to P_O_Data<10>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.473 0.534 Mtrien_P_O_Data_1
(Mtrien_P_O_Data_1)
OBUFT:T->O 3.957 P_O_Data_10_OBUFT
(P_O_Data<10>)
----------------------------------------
Total 4.964ns (4.430ns logic, 0.534ns route)
(89.2% logic, 10.8% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 31 / 31
-------------------------------------------------------------------------
Delay: 6.415ns (Levels of Logic = 3)
Source: P_I_adress<0> (PAD)
Destination: P_O_A0 (PAD)
Data Path: P_I_adress<0> to P_O_A0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.965 0.765 P_I_adress_0_IBUF
(P_I_adress_0_IBUF)
LUT3:I0->O 1 0.195 0.534 P_O_A01 (P_O_A0_OBUF)
OBUF:I->O 3.957 P_O_A0_OBUF (P_O_A0)
----------------------------------------
Total 6.415ns (5.117ns logic, 1.298ns route)
(79.8% logic, 20.2% route)
=========================================================================
CPU : 13.14 / 14.00 s | Elapsed : 13.00 / 14.00 s
-->
Total memory usage is 192560 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 20 ( 0 filtered)
Number of infos : 5 ( 0 filtered)