Simple question about if statemets

Discussion in 'VHDL' started by gman, Dec 11, 2006.

  1. gman

    gman Guest

    Hello All,
    Assuming that all the following signal are std_logic, why isn't the
    following line illegal:

    if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    Term = '1' and Ready ='1') then


    The compiler says:
    near "and": expecting: ')'
    near "or": expecting: ')'

    The problem seems to go away if I pair up the operands into groups of
    two using parenthesis. Why doesn't the compiler apply
    order-of-operation rules and evaluate the boolean statement?

    Thanks.
     
    gman, Dec 11, 2006
    #1
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  2. gman a écrit :
    > Hello All,
    > Assuming that all the following signal are std_logic, why isn't the
    > following line illegal:
    >
    > if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    > Term = '1' and Ready ='1') then
    >
    >
    > The compiler says:
    > near "and": expecting: ')'
    > near "or": expecting: ')'
    >
    > The problem seems to go away if I pair up the operands into groups of
    > two using parenthesis. Why doesn't the compiler apply
    > order-of-operation rules and evaluate the boolean statement?


    Not sure for VHDL (I'am a beginer) but on most languages, both "or" and "and"
    have precedence on compare operators, so your expressions would be evaluated as:

    if ( PCI_Frame_n = ('0' or PCI_Trdy_n) = ( .....

    You must use :
    > if ( (PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0') or


    Be careful : the "and" operator have precedence on the "or". Writen like this,
    your full line will be evaluated as :

    if ( (PCI_Frame_n = '0') or
    ((PCI_Trdy_n ='0') and (Hit='1') and (Term='0')) or
    ((Term = '1') and (Ready ='1')) ) then

    Is it exactely that you want ?
    Be precise : time taken to type some parenthesis is never loosen !

    Pascal
     
    Pascal Peyremorte, Dec 11, 2006
    #2
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  3. gman

    gman Guest

    I'm familiar with the order of operation rules. I'm trying to get the
    boolean statement to evaluate as written i.e. the ANDs first (from left
    to right) and then the ORs (from left to right). Regardless of the
    order of operation, why does the compiler generate syntax errors?

    Regards,

    -Ali

    Pascal Peyremorte wrote:
    > gman a écrit :
    > > Hello All,
    > > Assuming that all the following signal are std_logic, why isn't the
    > > following line illegal:
    > >
    > > if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    > > Term = '1' and Ready ='1') then
    > >
    > >
    > > The compiler says:
    > > near "and": expecting: ')'
    > > near "or": expecting: ')'
    > >
    > > The problem seems to go away if I pair up the operands into groups of
    > > two using parenthesis. Why doesn't the compiler apply
    > > order-of-operation rules and evaluate the boolean statement?

    >
    > Not sure for VHDL (I'am a beginer) but on most languages, both "or" and "and"
    > have precedence on compare operators, so your expressions would be evaluated as:
    >
    > if ( PCI_Frame_n = ('0' or PCI_Trdy_n) = ( .....
    >
    > You must use :
    > > if ( (PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0') or

    >
    > Be careful : the "and" operator have precedence on the "or". Writen like this,
    > your full line will be evaluated as :
    >
    > if ( (PCI_Frame_n = '0') or
    > ((PCI_Trdy_n ='0') and (Hit='1') and (Term='0')) or
    > ((Term = '1') and (Ready ='1')) ) then
    >
    > Is it exactely that you want ?
    > Be precise : time taken to type some parenthesis is never loosen !
    >
    > Pascal
     
    gman, Dec 11, 2006
    #3
  4. gman wrote:

    > I'm familiar with the order of operation rules. I'm trying to get the
    > boolean statement to evaluate as written i.e. the ANDs first (from left
    > to right) and then the ORs (from left to right). Regardless of the
    > order of operation, why does the compiler generate syntax errors?


    Coming from a C background, I've noticed that VHDL compilers sometimes
    require what I consider 'superfluous' bracketing as well. I've never
    bothered to look into it, I just add parentheses and keep going...

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Dec 12, 2006
    #4
  5. gman schrieb:


    > if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    > Term = '1' and Ready ='1') then



    The compiler is as confused as me. Do you mean

    if ( (PCI_Frame_n = '0' or PCI_Trdy_n ='0') and Hit='1' and Term='0' or
    (Term = '1' and Ready ='1') ) then

    or

    if ( PCI_Frame_n = '0' or (PCI_Trdy_n ='0' and Hit='1' and Term='0') or
    (Term = '1' and Ready ='1') ) then

    or something else? There is no left-to-right elavuation in VHDL as in C.

    Ralf
     
    Ralf Hildebrandt, Dec 12, 2006
    #5
  6. gman

    gman Guest

    What I'm trying to do is this in boolean:

    !PCI_Frame_n + !PCI_Trdy_n*Hit* !Term+Term*Ready


    Ralf Hildebrandt wrote:
    > gman schrieb:
    >
    >
    > > if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    > > Term = '1' and Ready ='1') then

    >
    >
    > The compiler is as confused as me. Do you mean
    >
    > if ( (PCI_Frame_n = '0' or PCI_Trdy_n ='0') and Hit='1' and Term='0' or
    > (Term = '1' and Ready ='1') ) then
    >
    > or
    >
    > if ( PCI_Frame_n = '0' or (PCI_Trdy_n ='0' and Hit='1' and Term='0') or
    > (Term = '1' and Ready ='1') ) then
    >
    > or something else? There is no left-to-right elavuation in VHDL as in C.
    >
    > Ralf
     
    gman, Dec 12, 2006
    #6
  7. gman wrote:
    > What I'm trying to do is this in boolean:
    >
    > !PCI_Frame_n + !PCI_Trdy_n*Hit* !Term+Term*Ready


    Just set brackets to force the evaluation to the desired operator
    precedence.

    Ralf
     
    Ralf Hildebrandt, Dec 12, 2006
    #7
  8. gman

    Andy Guest

    VHDL does not allow parallel combinations of AND and OR in expressions.
    You must use parentheses to specify the operation precedence you want.

    Think about it; if we had a hard time trying to figure out what you
    wanted, so would some poor sap that will have to maintain your design
    in the future.

    AND/OR precedence errors are a common error source in most programming,
    so VHDL just forces you to explicitly tell it what you want.

    Andy


    gman wrote:
    > What I'm trying to do is this in boolean:
    >
    > !PCI_Frame_n + !PCI_Trdy_n*Hit* !Term+Term*Ready
    >
    >
    > Ralf Hildebrandt wrote:
    > > gman schrieb:
    > >
    > >
    > > > if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    > > > Term = '1' and Ready ='1') then

    > >
    > >
    > > The compiler is as confused as me. Do you mean
    > >
    > > if ( (PCI_Frame_n = '0' or PCI_Trdy_n ='0') and Hit='1' and Term='0' or
    > > (Term = '1' and Ready ='1') ) then
    > >
    > > or
    > >
    > > if ( PCI_Frame_n = '0' or (PCI_Trdy_n ='0' and Hit='1' and Term='0') or
    > > (Term = '1' and Ready ='1') ) then
    > >
    > > or something else? There is no left-to-right elavuation in VHDL as in C.
    > >
    > > Ralf
     
    Andy, Dec 12, 2006
    #8
  9. gman

    Ale Brewer Guest

    "gman" <> wrote in news:1165873311.697175.252830@
    79g2000cws.googlegroups.com:

    > Hello All,
    > Assuming that all the following signal are std_logic, why isn't the
    > following line illegal:
    >
    > if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
    > Term = '1' and Ready ='1') then
    >
    >
    > The compiler says:
    > near "and": expecting: ')'
    > near "or": expecting: ')'
    >
    > The problem seems to go away if I pair up the operands into groups of
    > two using parenthesis. Why doesn't the compiler apply
    > order-of-operation rules and evaluate the boolean statement?
    >
    > Thanks.
    >


    It is because AND and OR are boolean operators.


    if (( PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0')
    or (Term = '1') and (Ready ='1')) then

    should compile

    --
    Posted via a free Usenet account from http://www.teranews.com
     
    Ale Brewer, Jan 10, 2007
    #9
  10. gman

    Andy Guest

    Nope, AND and OR are defined for std_logic too. However, the result is
    still a std_logic, and thus the entire expression must be compared to
    '1' or '0' to return a boolean which is required in the IF condition.

    if (not pci_frame_n or (not pci_trdy_n and hit and not term) or (term
    and ready)) = '1' then

    No final, all-enclosing parentheses are required either.

    Andy

    Ale Brewer wrote:
    >
    > It is because AND and OR are boolean operators.
    >
    >
    > if (( PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0')
    > or (Term = '1') and (Ready ='1')) then
    >
    > should compile
    >
    > --
    > Posted via a free Usenet account from http://www.teranews.com
     
    Andy, Jan 10, 2007
    #10
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