SPI, I2C and CPLD

[john]

Hi,

I am interfacing a CPLD with the ADC AD 7691's via SPI Bus. The ADC
Analog input is connected to an 16 channel output Multiplexer.

I am planing to use only Eight channels of the multiplexer and ADC
sampling rate of 96KHz whcih means that I can only sample at 12KHz
signal for each channel.

Now, the ADC output 18 bit data will be receieved by the wireless chip
nRF24Z1 via I2C bus.

My questions are as follows,

1. How will I approcah this project?
2. Is there I2C VHDL already working component available that I can
use?
3. Is SPI interface already available written in VHDL?
4. I do not know that what clcok speed, the CPLD will be wriritng the
data to the nRF24z1 chip. But it might be different form the ADC
clcok. now in that case how can I achieve the synchronization between
the two different clocks? FIFO!!

Thanks
John

 

[Rich Webb]

Hi,

I am interfacing a CPLD with the ADC AD 7691's via SPI Bus. The ADC
Analog input is connected to an 16 channel output Multiplexer.

I am planing to use only Eight channels of the multiplexer and ADC
sampling rate of 96KHz whcih means that I can only sample at 12KHz
signal for each channel.

Now, the ADC output 18 bit data will be receieved by the wireless chip
nRF24Z1 via I2C bus.

My questions are as follows,

1. How will I approcah this project?

What drives this particular choice of architecture? At first glance, a
microcontroller would appear to be more suitable than a CPLD but there
may be other considerations that are not immediately apparent.

2. Is there I2C VHDL already working component available that I can
use?
Yes.

3. Is SPI interface already available written in VHDL?
Yes.

4. I do not know that what clcok speed, the CPLD will be wriritng the
data to the nRF24z1 chip. But it might be different form the ADC
clcok. now in that case how can I achieve the synchronization between
the two different clocks? FIFO!!

Yes.