SRL and ROL

Discussion in 'VHDL' started by Chris Connelly, Aug 3, 2004.

1. Chris ConnellyGuest

Please excuse the probable simplicity of this question.

I'm trying to use ROL and SRL logical operators and I can't seem to
find the correct syntax.

I have a bit_vector(31 downto 0) called 'tx' , now all I want to do is
rotate the vector to the left and pick of bit(0).
As I said I've tried a few arrangements ie. tx ROL 1 and ROL tx but
nothing seems to work.

Can someone let me know what the syntax is to do this simple task.

TIA

Chris

Chris Connelly, Aug 3, 2004

2. Egbert MolenkampGuest

entity test is
port (A : in bit_vector(31 downto 0);
p : in integer;
B : out bit_vector(31 downto 0));
end test;

architecture behavior of test is

begin
B <= A Rol p;
end behavior;

Egbert Molenkamp

"Chris Connelly" <> wrote in message
news:...
> Please excuse the probable simplicity of this question.
>
> I'm trying to use ROL and SRL logical operators and I can't seem to
> find the correct syntax.
>
> I have a bit_vector(31 downto 0) called 'tx' , now all I want to do is
> rotate the vector to the left and pick of bit(0).
> As I said I've tried a few arrangements ie. tx ROL 1 and ROL tx but
> nothing seems to work.
>
> Can someone let me know what the syntax is to do this simple task.
>
> TIA
>
> Chris

Egbert Molenkamp, Aug 3, 2004

3. Ralf HildebrandtGuest

Chris Connelly wrote:

> I'm trying to use ROL and SRL logical operators and I can't seem to
> find the correct syntax.
>
> I have a bit_vector(31 downto 0) called 'tx' , now all I want to do is
> rotate the vector to the left and pick of bit(0).
> As I said I've tried a few arrangements ie. tx ROL 1 and ROL tx but
> nothing seems to work.

tx_rolled(31 downto 0) <= tx(0) & tx (31 downto 1);

works indipendent from used libraries, but is fixed as can bee seen.

Ralf

Ralf Hildebrandt, Aug 3, 2004
4. Mike TreselerGuest

(Chris Connelly) wrote in message news:<>...
> Please excuse the probable simplicity of this question.
>
> I'm trying to use ROL and SRL logical operators and I can't seem to
> find the correct syntax.
>
> I have a bit_vector(31 downto 0) called 'tx' , now all I want to do is
> rotate the vector to the left and pick of bit(0).
> As I said I've tried a few arrangements ie. tx ROL 1 and ROL tx but
> nothing seems to work.

Consider using rotate_left from the
ieee.numeric_std library as shown below.

-- Mike Treseler

-----------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rotate is
-- Mike Treseler Tue Aug 3 09:52:10 2004

generic (len : positive := 32);

port (clk : in std_ulogic;
rst : in std_ulogic;
rot : in std_ulogic; -- rotate or init
tx : out std_ulogic);

end entity rotate;

architecture synth of rotate is

begin -- architecture sim
sh : process (clk, rst) is
variable tx_v : unsigned(len-1 downto 0);
begin -- process sh
if rst = '1' then
tx_v := (others => '0');
tx <= tx_v(0);
elsif rising_edge(clk) then
if rot = '1' then
tx_v := rotate_left(tx_v, 1); -- rotate data
tx <= tx_v(0); -- pick off bit 0
else
tx_v := x"13701248"; -- init data
end if;
end if;
end process sh;

end architecture synth;

Mike Treseler, Aug 3, 2004