For a quick tutorial on VHDL types and conversions see my
MAPLD paper, VHDL Math Tricks of the Trade. It is available
at
http://www.synthworks.com/papers
Ben>>Is there a built in function that can convert a STD_LOGIC_VECTOR type
Ben>>to an 'unsigned' type?
Allan> No, there are no "built in" functions that do that.
Ironically the type casting you show is called implicit type conversion
and is built-in to the language.
To convert from an array to an integer requires a type conversion
function that is defined in one of the packages.
(BTW, std_logic_vector and unsigned aren't part of the the VHDL
language.)
What is VHDL? Is it IEEE 1076 or is it IEEE 1076 + the related
standards that were developed to support VHDL.
-- this won't work (arith isn't (and shouldn't be) defined for slv)
slv <= slv + 1;
This is a purist point of view.
If you include the package std_logic_unsigned it will work:
use ieee.std_logic_unsigned.all ; -- shareware from synopsys
This package overloads numeric operators allow std_logic_vector
to have an unsigned interpretation. Long term it is likely
that this package will be replaced by a similar package from
the IEEE 1076.3 working group.
There are three methodologies with respect to usage of the
std_logic_unsigned arithemetic package:
1) For math, only use types signed and unsigned from numeric_std
2) Permitted to use std_logic_unsigned for incrementers/counters
and testbenches. Use numeric_std for all other math.
3) Use std_logic_unsigned for any unsigned math.
Personally I use either 2 (preferred) or 1. 1 becomes
painful for some testbenches. In a testbench you often
need to do something like increment a std_logic_vector
typed address bus. Here the numerous type casting becomes
painful.
Recommendation: don't use the package std_logic_signed.
Like the other things, this is an opinion. While I am not
a purist, I also don't like chaos.
Cheers,
Jim
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Jim Lewis
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SynthWorks Design Inc.
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Expert VHDL Training for Hardware Design and Verification
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