Store register instantiation

Discussion in 'VHDL' started by Massi, Apr 2, 2009.

  1. Massi

    Massi Guest

    Hi everyone, I'm really new to the vhdl world, so I apologize if my
    question is trivial. I'm working on xilinx Virtex 5 FPGA with ISE
    10.1. My module receives a 16 bit input data and I would like to store
    it into a register, without using any RAM block. Which is the simplest
    way to instantiate such a simple store register? Is there any
    primitive?
    Thanks in advance.
     
    Massi, Apr 2, 2009
    #1
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  2. Massi wrote:
    > Hi everyone, I'm really new to the vhdl world, so I apologize if my
    > question is trivial. I'm working on xilinx Virtex 5 FPGA with ISE
    > 10.1. My module receives a 16 bit input data and I would like to store
    > it into a register, without using any RAM block. Which is the simplest
    > way to instantiate such a simple store register? Is there any
    > primitive?
    > Thanks in advance.


    A simple FF should do the trick:


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;


    ENTITY example IS
    PORT
    (
    clk : std_logic;
    data_in : std_logic_vector(15 DOWNTO 0)
    );
    END ENTITY example;


    ARCHITECTURE rtl OF example IS
    SIGNAL data_in_i : std_logic_vector(15 DOWNTO 0);
    BEGIN
    input_reg: PROCESS IS
    BEGIN
    WAIT UNTIL clk = '1';
    data_in_i <= data_in;
    END PROCESS input_reg;
    END ARCHITECTURE rtl;


    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Apr 2, 2009
    #2
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  3. Massi

    Andy Guest

    On Apr 2, 10:12 am, Pieter Hulshoff <> wrote:
    >   input_reg: PROCESS IS
    >   BEGIN
    >     WAIT UNTIL clk = '1';
    >     data_in_i <= data_in;
    >   END PROCESS input_reg;


    I stronly agree with inferring a register, rather than instantiating
    one. Instantiated primitive names are often not portable across
    differen devices.

    There are lots of ways to infer a register; the simplest is probably:

    data_in_i <= data_in when rising_edge(clk); -- concurrent statement,
    no process needed

    Where data_in_i is the output of the inferred register.

    However, I believe a more standard (and more appropriate for new
    users) process template for inferring one or more registers is as
    follows:

    input_reg: process (clk) is
    begin
    if rising_edge(clk) then
    data_in_i <= data_in;
    end if;
    end process;

    The rising_edge() function specifically avoids simulation problems
    from strange transitions on the clock signal. Pieter's template could
    be improved in this regard by using "wait until rising_edge(clk);"

    The wait statement template is more difficult to add an asynchronous
    reset input.

    For an asynchronously reset register:

    input_reg: process (clk, rst) is
    begin
    if rst = '1' then -- active high reset
    data_in_i <= (others -> '0');
    elsif rising_edge(clk) then
    data_in_i <= data_in;
    end if;
    end process;

    Or, in the concurrent template:

    data_in_i <= (others => '0') when rst = '1'
    else data_in when rising_edge(clk);

    All of these are roughly equivalent if all you need to do is insert a
    register between two other entities, etc. If you are also specifying
    the logic that is in between the registers, the process templates are
    much better suited, since you can describe the logic and the registers
    in the same process, at the same time.

    Andy
     
    Andy, Apr 2, 2009
    #3
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