Switch level simulation package

Discussion in 'VHDL' started by Mike Bolotski, Aug 18, 2003.

  1. Hello.

    I see this question coming up once a year or so, but I haven't seen a
    general enough solution.

    I have a VHDL-based, transistor-level netlist created by ViewDraw. I'd
    like to simulate it in VHDL for a variety of reasons.

    Is there a decent model for NFETs and PFETs that handles bidirectional
    switches, capacitive nodes (for dynamic logic), etc?

    There are tantalizing possibilities in Ashenden's book, but I'd rather
    not reinvent the wheel. All articles that I'm able to read give a
    one-page overview but don't provide the full details for the mos
    package.

    Help?

    PS. Ben Cohen's models are pretty, but have a failure mode...
    Mike Bolotski, Aug 18, 2003
    #1
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  2. Mike Bolotski

    VhdlCohen Guest

    >I see this question coming up once a year or so, but I haven't seen a
    >general enough solution.
    >
    >I have a VHDL-based, transistor-level netlist created by ViewDraw. I'd
    >like to simulate it in VHDL for a variety of reasons.
    >
    >Is there a decent model for NFETs and PFETs that handles bidirectional
    >switches, capacitive nodes (for dynamic logic), etc?
    >
    >There are tantalizing possibilities in Ashenden's book, but I'd rather
    >not reinvent the wheel. All articles that I'm able to read give a
    >one-page overview but don't provide the full details for the mos
    >package.
    >
    >Help?
    >
    >PS. Ben Cohen's models are pretty, but have a failure mode.


    Your best bet is to use Verilog if you can get the netlist to be created by
    your tool.
    VHDL is weak on switch level modeling.
    By the way, mixed mode simulation with VHDL models for everything and Verilog
    models for the switches does NOT work im either ModelSim or NcSim.
    It might be a lot of work, but you could write a script or code to translate
    VHDL netlist to Verilog.
    Best of luck!!!
    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
    VhdlCohen, Aug 19, 2003
    #2
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