Switching Frequency of FPGA

[raullim7]

Hi, may i know if it is possible to double the switching frequency of
the FPGA via VHDL? If possible, what are the methods available? Thanks

 

[Mike Treseler]

Hi, may i know if it is possible to double the switching frequency of
the FPGA via VHDL? If possible, what are the methods available? Thanks

Most FPGAs have PLLs or DLLs that could do this,
but consider a synchronous design using
a faster clock.

-- Mike Treseler

 

[Dwayne Dilbeck]

That is going to depend on the FPGA and synthesis tool. In some cases, there
is a register in the fpga that determines the PLL configuration. If the
FPGa lets you interface to the internal FPGA register, the vendor will have
a white paper describing the process. IT usually involes a synthesis
directive in the comments next to the register definition. This tells the
Synthesizer to map register "ABC" to the fpga's internal register rather
than a set of flip flops.

You fpga vendor should have some FAEs that can help. If you are using
Xilinx FPGAs I might be able to get some contacts for you from my friend.
But no garantees. She hasn't worked as a Xilinx FAE for 4 years.

 

[raullim7]

Most FPGAs have PLLs or DLLs that could do this,
but consider a synchronous design using
a faster clock.

    -- Mike Treseler

hi, how can i get a faster clock?

 

[Mike Treseler]

hi, how can i get a faster clock?

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=CTX318LVTR-ND

 

[raullim7]

formerly, i used the rising edge of the clock pulse to implement my
design. in this, i got a 100% duty cycle.

then i used the falling edge of the clock pulse to enhance the design.
in this, i got a 50% duty cycle.

now, i want to achieve 25% duty cycle. but i have used up all the
triggering edges of the clock pulse. how can i further reduce the 50%
duty cycle to 25%?? please help. thanks

 

[KJ]

formerly, i used the rising edge of the clock pulse to implement my
design. in this, i got a 100% duty cycle.

then i used the falling edge of the clock pulse to enhance the design.
in this, i got a 50% duty cycle.

now, i want to achieve 25% duty cycle. but i have used up all the
triggering edges of the clock pulse. how can i further reduce the 50%
duty cycle to 25%?? please help. thanks

First off, using both edges of the clock is dicey because many times you
don't get really good control of the duty cycle of that clock, plus if you
don't have a voltage swing that is symmetric to the actual voltage threshold
of the device than you'll have additional skew problems...then there are
differences in slew rate between rising and falling edges, the list goes on
and if your timing analysis is based on the skew between rising and falling
edges being anywhere actually near 50% you'll be in for a load of trouble
down the line.

To get 2x, 4x, whateverx you should be using a phase-locked loop. This can
be either a discrete part on your board (if your programmable part doesn't
have such a beast) or internal to the device (most newer FPGAs have them).

KJ

 

[kays_f]

What kind of an FPGA are you using? For example I used Virtex4 and
VirtexE series and they have dedicated clock resources such as DCM. So
that you can multiply and divide the clock with any value you want.

 

[raullim7]

What kind of an FPGA are you using? For example I used Virtex4 and
VirtexE series and they have dedicated clock resources such as DCM. So
that you can multiply and divide the clock with any value you want.

i am using spartan 3 XEM3010.. i tried using DCM before but there isnt
any guide to it and i messed it all up.. end up, i have to reinstall
the software..

 

[raullim7]

i am using spartan 3 XEM3010.. i tried using DCM before but there isnt
any guide to it and i messed it all up.. end up, i have to reinstall
the software..

i just checked that even if i am able to activate DCM, i am still not
able to use the doubled clock frequency in my design bcos the part
"process(clk, reset)", these two signals have to be an IN signal
rather than an OUT signal. CLK2X is an OUT signal and therefore i will
not be able to use it.

regarding PLL and DLL, i checked the datasheet of my FPGA and infos
are limited. how can i use the PLL or DLL to generate a faster clock?
i really have no idea about it.. please help.. thanks

 

[Mark McDougall]

i just checked that even if i am able to activate DCM, i am still not
able to use the doubled clock frequency in my design bcos the part
"process(clk, reset)", these two signals have to be an IN signal
rather than an OUT signal. CLK2X is an OUT signal and therefore i will
not be able to use it.

May I humbly suggest that you take a step backwards for a while - forget
synthesising your own design and perhaps study a few simple designs,
ideally those implemented in schematic. IMHO you're missing a few
fundamental concepts that you really need to grasp before embarking on
your own designs - otherwise you'll be banging your head against a brick
wall and/or, as you've already exhibited, get into the habit of using bad
design practises.

regarding PLL and DLL, i checked the datasheet of my FPGA and infos
are limited. how can i use the PLL or DLL to generate a faster clock?
i really have no idea about it.. please help.. thanks

For the record, generally you'll feed the external clock pin into the
input of the PLL/DLL, configure it with your desired multiplier/divisor
factors (amongst other parameters) and use the output(s) to clock the
remainder of your design. Typically you'll have a choice of a wide range
of frequencies for the output, ranging from a few MHz to a few hundred
MHz, regardless of your input clock frequency. Caveat - there are
limitations on the PLL/DLL as per the datasheet.

Regards,